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www.gennum.com gs4901b/GS4900B sd clock and timing generator with genlock gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 1 of 95 key features video clock synthesis ? pre-programmed for 4 video clock periods (14.32 mhz, 27 mhz, 36 mhz, and 54 mhz) ? accuracy of free-running clock frequency limited only by crystal reference ? one differential and two single-ended video clock outputs ? each clock may be individually delayed for skew control ? video output clock may be directly connected to gennum?s serializers for a smpte-compliant sdi output audio clock synthesis (gs4901b only) ? three audio clock outputs ? generates any audio clock up to 512*96khz ? pre-programmed for 7 audio clocks timing generation ? generates up to 8 timing signals at a time ? choose from 9 pre-programmed timing signals: h and v sync and blanking, f sync, f digital, afs (gs4901b only), display enable, 10fid, and up to 4 user-defined timing signals ? pre-programmed to generate timing for 9 different video formats genlock capability ? clocks may be free-running or genlocked to an input reference with a variable offset step size of 100-200ps (depending on exact clock frequency) ? variable timing offset step size of 100-200ps up to one frame ? output may be cross-locked to a different input reference ? freeze operation on loss of reference ? optional crash or drift lock on application of reference ? automatic input format detection general features ? reduces design complexity and saves board space - 9mm x 9mm package plus crystal reference replaces multiple vcxos, plls and timing generators ? pb-free and rohs compliant ? low power operation typically 300mw ? 1.8v core and 1.8v or 3.3v i/o power supplies ? 64-pin qfn package applications ? video cameras; digital audio and/or video recording/play back devices; digital audio and/or video processing devices; computer/video displays; dvd/mpeg devices; digital set top boxes; video projectors; high definition video systems; multi-me dia pc applications description the gs4901b is a highly fl exible, digitally controlled clock synthesis circuit and timing generator with genlock capability. it can be us ed to genera te video and audio clocks and timing sig nals, and allows multiple devices to be genlocked to an input reference. the GS4900B includes all the features of the gs4901b, but does not offer audio cloc ks or afs pulse generation. the gs4901b/GS4900B will reco gnize input reference signals conforming to 36 di fferent video standards, and will genlock the output timi ng informat ion to the incoming reference. the gs4901b/GS4900B supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. the user may select to output one of 4 different video sample clock rates. the chosen clock frequency can be further divided using internal dividers, and is available on two video clock outputs and one lvds video clock output pair. the video clocks are frequency and phased-locked to the horizontal timing reference, and can be individually delayed with respect to the timing outputs for clock skew control. eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 9 different video formats: hsync, hblanking, vsync, vblanking, f sync, f digital, afs (gs4901b only), de, and 10fid. these timing outputs may be locked to the input reference signal for genlock timing and may be phase adjusted via internal registers. in addition, the gs4901b provides three audio sample clock outputs that can produc e audio clocks up to 512fs with fs ranging from 9.7khz to 96khz. audio to video phasing is accomplished by an external 10fid input reference, a 10fid signal specified via internal registers, or a user-programmed audio frame sequence. the gs4901b/GS4900B is pb-free, and the encapsulation compound does not contain halogenated flame retardant (rohs compliant).
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 2 of 95 gs4901b functional block diagram clock synthesis and control flywheel and video timing generator input reference rate identification and control crosspoint video clock divide audio clock divide 3x video clock delay adjust application programming interace hsync vsync fsync 10fid lock_lost ref_lost vid_std[5:0] asr_sel[2:0] x1 x2 timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 pclk1 pclk2 pclk3 aclk1 aclk2 aclk3 pclk3 genlock pclk aclk_512 aclk_384 10fid de h blanking h sync user[4:1] ref_rate 27mhz clock phase adjust jtag/host sclk_tclk sdin_tdi sdout_tdo cs_tms v blanking v sync f digital f sync afs
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 3 of 95 GS4900B functional block diagram clock synthesis and control flywheel and video timing generator input reference rate identification and control crosspoint video clock divide 3x video clock delay adjust application programming interace hsync vsync fsync 10fid ref_lost vid_std[5:0] x1 x2 timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 pclk1 pclk2 pclk3 pclk3 genlock pclk 10fid de h blanking h sync user[4:1] ref_rate 27mhz clock phase adjust jtag/host sclk_tclk sdin_tdi sdout_tdo cs_tms v blanking v sync f digital f sync lock_lost
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 4 of 95 contents key features.................................................................................................................1 applications................................................................................................................... 1 description .................................................................................................................... 1 1. pin out ..................................................................................................................... .8 1.1 gs4901b pin assignment ... .............. .............. .............. .............. ........... ........8 1.2 GS4900B pin assignment ... .............. .............. .............. .............. ........... ........9 1.3 pin descriptions ............................................................................................10 1.4 pre-programmed recognized video standards ...........................................20 1.5 output timing signals ...................................................................................24 2. electrical characteristics .........................................................................................28 2.1 absolute maximum ratings ..........................................................................28 2.2 dc electrical characteristics ............. ...........................................................28 2.3 ac electrical characteristics .............. ...........................................................30 2.4 solder reflow profiles ...................................................................................33 3. detailed description .................................. ..............................................................34 3.1 functional overview .....................................................................................34 3.2 modes of operation ....... .............. .............. .............. .............. .............. .........34 3.2.1 genlock mode......................................................................................35 3.2.2 free run mode....................................................................................38 3.3 output timing format selection .......... .........................................................39 3.4 input reference signals ................................................................................40 3.4.1 hsync, vsync, and fsync............. .............. .............. ........... .........40 3.4.2 10fid ...................................................................................................41 3.4.3 automatic polarity recognition ...... ......................................................41 3.5 reference format de tector ..........................................................................42 3.5.1 horizontal and vertical timing characteristic measurements .............42 3.5.2 input reference validity................. ......................................................43 3.5.3 behaviour on loss and re-acquisi tion of the reference signal..........44 3.5.4 allowable frequency drift on the re ference .......................................46 3.6 genlock .........................................................................................................46 3.6.1 adjustable locking time................ ......................................................47 3.6.2 adjustable loop bandwidth .................................................................48 3.6.3 locking to digital timing from a de serializer ......................................51 3.7 clock synthesis ............................................................................................52 3.7.1 video clock synthesis .........................................................................52 3.7.2 audio clock synthesis (gs4901b onl y) ..............................................53 3.8 video timing generator . ...............................................................................57 3.8.1 10 field id pulse .................................................................................57 3.8.2 audio frame synchronizing pulse (gs4901b only) ............................58 3.8.3 user_1~4...........................................................................................59
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 5 of 95 3.8.4 timing_out pins...............................................................................61 3.9 extended audio mode for hd demux using the gennum audio core .........62 3.10 gspi host interface ....................................................................................63 3.10.1 command word description........... ...................................................64 3.10.2 data read and write timing ....... ......................................................64 3.10.3 configuration and status registers ...................................................66 3.11 jtag ...........................................................................................................87 3.12 device power-up ........................................................................................88 3.12.1 power supply sequencing.............. .............. .............. .............. .........88 3.13 device reset ...............................................................................................88 4. application reference design .................................................................................89 4.1 gs4901b typical application circuit ... .............. ............ ........... ........... .........89 4.2 GS4900B typical application circuit ... .............. ............ ........... ........... .........90 5. references & relevant standards ..........................................................................91 6. package & ordering information .............................................................................92 6.1 package dimensions ....................................................................................92 6.2 recommended pcb footprint ............. .............. ............ ........... ........... .........93 6.3 packaging data .............................................................................................93 6.4 ordering information .....................................................................................94 7. revision history ......................................................................................................95
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 6 of 95 list of figures gs4901b functional block diagram................. .............. .............. ............ ........... ....... 2 GS4900B functional block diagram................. .............. .............. ............ ........... ....... 3 figure 1-1: xtal1 and xtal2 reference circuits ....................................................19 figure 2-1: pclk to timing_out signal output timing ..........................................32 figure 2-2: maximum pb-free so lder reflow profile (preferred) ................................33 figure 2-3: standard pb solder reflow profile ............ .............. ........... ........... .........33 figure 3-1: sd-hd calculation ..................... ..............................................................37 figure 3-2: output accuracy and modes of o peration ...............................................39 figure 3-3: example hsync, vsync , and fsync analog input timing from a sync separator .......... .............. .............. .............. ............ ........... ........... .........40 figure 3-4: example h blanking, v blanking, and f digital input timing from an sdi deserializer ............................................................................................40 figure 3-5: 10fid input timing .................... ..............................................................41 figure 3-6: default 10fid output timing ...................................................................57 figure 3-7: optional 10fid output timing ...... .............. .............. ........... ........... .........58 figure 3-8: afs output timing ..................................................................................59 figure 3-9: user programmable output signal .......................................................60 figure 3-10: audio clock block diagram for hd demux operation ...........................62 figure 3-11: gspi application interface conn ection .................................................63 figure 3-12: command word format ........................................................................64 figure 3-13: data word format ...................... ...........................................................64 figure 3-14: gspi read mode timing ............ ...........................................................65 figure 3-15: gspi write mode timing ............ .............. .............. ........... ........... .........65 figure 3-16: in-circuit jtag ......................................................................................87 figure 3-17: system jtag .........................................................................................88
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 7 of 95 list of tables table 1-1: pin descriptions ........................................................................................ 10 table 1-2: recognized video standards ................................................................... 21 table 1-3: output timing signals............................................................................... 24 table 2-1: dc electrical characteristics .......... .......................................................... 28 table 2-2: ac electrical characteristics........ ............................................................. 30 table 2-3: suggested external crystal specific ation ................................................. 32 table 3-1: clock_phase_offset[15:0] encoding scheme .......................................... 36 table 3-2: ambiguous standard identification .. ......................................................... 44 table 3-3: max_ref_delta encoding scheme ...... ..................................................... 46 table 3-4: cross-reference genlock table ...... .......................................................... 47 table 3-5: integer constant va lue ............................................................................. 50 table 3-6: video clock phase adjustment host settings .......................................... 53 table 3-7: audio sample rate select ........................................................................ 54 table 3-8: audio clock divider................................................................................... 54 table 3-9: encoding scheme for afs_reset_wi ndow ............................................. 55 table 3-10: audio sampling frequency to video frame rate synchronization ........ 56 table 3-11: crosspoint select .......................... .......................................................... 61 table 3-12: gspi timing parame ters ........................................................................ 65 table 3-13: configuration and status register s ........................................................ 66 table 5-1: references & relevant standards.. .............. .............. .............. ........... ..... 91
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 8 of 95 1. pin out 1.1 gs4901b pin assignment lock_lost genlock 64-pin qfn (top view) 1 ref_lost vid_pll_vdd vid_pll_gnd xtal_vdd x1 x2 xtal_gnd core_gnd analog_vdd nc analog_gnd aud_pll_gnd aud_pll_vdd 10fid hsync io_vdd sdout_tdo sdin_tdi sclk_tclk phs_gnd phs_vdd pclk1&2_vdd pclk1&2_gnd pclk1 io_vdd pclk2 lvds/pclk3_gnd pclk3 lvds/pclk3_vdd core_vdd timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 io_vdd asr_sel0 asr_sel1 asr_sel2 io_vdd aclk3 aclk2 aclk1 vid_std5 core_vdd vid_std0 vid_std4 vid_std3 vid_std2 vid_std1 nc fsync io_vdd vsync reset cs_tms pclk3 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 nc ground pad (bottom of package) jtag/host gs4901b
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 9 of 95 1.2 GS4900B pin assignment lock_lost genlock GS4900B 64-pin qfn (top view) 1 ref_lost vid_pll_vdd vid_pll_gnd xtal_vdd x1 x2 xtal_gnd core_gnd analog_vdd nc analog_gnd 10fid hsync io_vdd sdout_tdo sdin_tdi sclk_tclk phs_gnd phs_vdd pclk1&2_vdd pclk1&2_gnd pclk1 io_vdd pclk2 lvds/pclk3_gnd pclk3 lvds/pclk3_vdd core_vdd timing_out_8 timing_out_7 timing_out_6 timing_out_5 timing_out_4 timing_out_3 timing_out_2 timing_out_1 io_vdd io_vdd nc nc nc vid_std5 core_vdd vid_std0 vid_std4 vid_std3 vid_std2 vid_std1 nc fsync io_vdd vsync reset cs_tms pclk3 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 nc ground pad (bottom of package) jtag/host analog_gnd analog_gnd analog_gnd analog_gnd analog_gnd
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 10 of 95 1.3 pin descriptions table 1-1: pin descriptions pin number name timing type description 1 lock_lost non synchronous output status signal output signal levels are lvcmos/lvttl compatible. this pin will be high if the output is not genlocked to the input. the gs4901b/GS4900B monitors the out put pixel/line counters, as well as the internal lock status from the genlock block and asserts lock_lost high if it is determined that the output is not genlocked to the input. this pin will be low if the device successfully genlocks the output clock and timing signals to the input reference. if lock_lost is low, the referenc e timing generator outputs will be phase locked to the detected referenc e signal, producing an output in accordance with the video standard se lected by the vid_std[5:0] pins. 2 ref_lost non synchronous output status signal output signal levels are lvcmos/lvttl compatible. this pin will be high if: ? no input reference signal is applied to the device; or ? the input reference applied does not meet the minimum/maximum timing requirements described in section 3.5.2 on page 43 . this pin will be low otherwise. if the reference signal is removed w hen the device is in genlock mode, ref_lost will go high and the gs4901b/GS4900B will enter freeze mode (see section 3.2.1.2 on page 38 ). 3 vid_pll_vdd ? power supply most positive power supply connect ion for the video clock synthesis internal block. connect to +1.8v dc. 4 vid_pll_gnd ? power supply ground connection for the video clock sy nthesis internal block. connect to gnd. 5 xtal_vdd ? power supply most positive power supply connection for the crystal buffer. connect to either +1.8v dc or +3.3v dc. note: connect to +3.3v for minimum output pclk jitter. 6x1 non synchronous input analog signal input connect to a 27mhz crystal or a 27mhz external clock source. see figure 1-1 . 7x2 non synchronous output analog signal output connect to a 27mhz crystal, or leave this pin open circuit if an external clock source is applied to pin 6. see figure 1-1 . 8xtal_gnd ? power supply ground connection for the crystal buffer. connect to gnd. 9 core_gnd ? power supply ground connection for core and i/o. solder to the ground plane of the application board. note: the core_gnd pin should be soldered to the same main ground plane as the exposed ground pad on the bottom of the device. 10 analog_vdd ? power supply most positive power supply connect ion for the analog input block. connect to +1.8v dc. 11, 20, 63 nc ? ? do not connect.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 11 of 95 12 analog_gnd ? power supply ground connection for the analog input block. connect to gnd. 13 aud_pll_gnd (gs4901b only) ? power supply ground connection for the audio clock synt hesis internal block. connect to gnd. analog_gnd (GS4900B only) ? power supply ground connection for the analog input block. connect to gnd. 14 aud_pll_vdd (gs4901b only) ? power supply most positive power supply connect ion for the audio clock synthesis internal block. connect to +1.8v dc. analog_gnd (GS4900B only) ? power supply ground connection for the analog input block. connect to gnd. 15 10fid non synchronous input reference signal input signal levels are lvcmos/lvttl compatible. the 10fid external reference signal is applied to this pin by the application layer. 10fid defines t he field in which the video and audio clock phase relationship is defined acco rding to smpte 318-m. it is also used to define a 3:2 video cadence. note: if the input reference format does not include a 10 field id signal, this pin should be held low. see section 3.4.2 on page 41 . 16 hsync non synchronous input reference signal input signal levels are lvcmos/lvttl compatible. the hsync external reference signal is applied to this pin by the application layer. when the gs4901b/g s4900b is operating in genlock mode, the device senses the polarity of the hsync input automatically, and references to the leading edge. this signal must adhere to one of the 36 defined video standards supported by the device. in this mode of operation, the hsync input provides a horizontal scanning reference signal. the hsync signal may have analog timing, such as from a sync separator, or may be digital such as from an sdi deserializer. section 1.4 on page 20 describes the 36 video formats recognized by the gs4901b/GS4900B. 17 vsync non synchronous input reference signal input signal levels are lvcmos/lvttl compatible. the vsync external reference signal is applied to this pin by the application layer. when the gs4901b/g s4900b is operating in genlock mode, the device senses the polarit y of the vsync input automatically, and references to the leading edge. this signal must adhere to one of the 36 defined video standards supported by the device. in this mode of operation, the vsync input provides a vertical scanning reference signal. the vsync signal may have analog timing, such as from a sync separator, or may be digital such as from an sdi deserializer. section 1.4 on page 20 describes the 36 video formats recognized by the gs4901b/GS4900B. 18, 31, 38, 50, 62 io_vdd ? power supply most positive power supply connect ion for the digital i/o signals. connect to either +1.8v dc or +3.3v dc. note: all five io_vdd pins must be powered by the same voltage. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 12 of 95 19 fsync non synchronous input reference signal input signal levels are lvcmos/lvttl compatible. the fsync external reference signal is applied to this pin by the application layer. the first field is defined as the field in which t he first broad pulse (also known as serration) is in the first half of a line. the fsync signal should be set high during the first field for sync-based references. then this signal must adhere to one of the 36 defined video standards supported by the device. in this mode of operation, the fsync input provides an odd/even field input reference. the fsync signal may have analog ti ming, such as from a sync separator, or may be digital such as from an sdi deserializer. section 1.4 on page 20 describes the 36 video formats recognized by the gs4901b/GS4900B. for blanking-based references, the fsync signal should be set high during the second field. note: if the input reference format does not include an f sync signal, this pin should be held low. 27, 25, 24, 23, 22, 21 vid_std[5:0] non synchronous input control signal inputs signal levels are lvcmos/lvttl compatible. video standard select. used to select the desired video fo rmat for video clock and timing signal generation. 4 different video sample clocks, as well as 9 different video format timing signal outputs may be selected using these pins. note: the vid_std[5:4] pins s hould be grounded by the application layer since these pins are not requir ed to select output video standards 1 to 10. for details on the supported video standards and video clock frequency selection, please see section 1.4 on page 20 . 26, 44 core_vdd ? power supply most positive power supply connecti on for the digital core. connect to +1.8v dc. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 13 of 95 28, 29, 30 aclk1 aclk2 aclk3 (gs4901b only) ? output clock signal outputs signal levels are lvcmos/lvttl compatible. audio output clock signals. aclk1, aclk2, and aclk3 present audio sample rate clock outputs to the application layer. by default, after system reset, the audi o clock output pins of the device provide clock si gnals as follows: aclk1 = 256fs aclk2 = 64fs aclk3 = fs, where fs is the fundamental sampling frequency. the fundamental sampling frequency is selected using asr_sel[2:0]. additional sampling frequencies may be programmed in the host interface. it is also possible to select different division ratios for each of the audio clock outputs by programming designated registers in the host interface. clock outputs of 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs and z bit are selectable on a pin-by-pin basis. note: aclk1-3 will have a 50% duty cy cle, unless fs is selected as 96khz and the host interface is configured such that one of the three aclk pins is set to output a clock si gnal at 192fs or 384fs. if this is the case, then a 512fs clock will have a 33% duty cycle. these signals will be high impedance when asr_sel[2:0] = 000b. nc (GS4900B only) ? ? do not connect. 32, 33, 34 asr_sel[2:0] (gs4901b only) non synchronous input control signal inputs signal levels are lvcmos/lvttl compatible. audio sample rate select. used to select the fundamental sampling frequency, fs, of the audio clock outputs. see table 3-7 . when asr_sel[2:0] = 000b, audio clock generation will be disabled and the aclk1 to aclk3 pins will be high impedance. in this case, aud_pll_vdd (pin 14) may be connected to gnd to minimize noise and power consumption. analog_gnd (GS4900B only) ? power supply ground connection for the analog input block. connect to gnd. 35 timing_out_1 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is h sync. the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 14 of 95 36 timing_out_2 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is h blanking. the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. 37 timing_out_3 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is v sync. the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. 39 timing_out_4 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is v blanking. the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. 40 timing_out_5 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is f sync. the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 15 of 95 41 timing_out_6 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is f digital. the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. 42 timing_out_7 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is 10 field id (10fid). the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. 43 timing_out_8 synchronous with pclk1 ~ pclk3 output timing signal output signal levels are lvcmos/lvttl compatible. selectable timing output. selectable from: h sync; h blanking; v sync; v blanking; f sync; f digital; display enable; 10 field id (film cadence); afs video/audio timing (gs4901b only); user_1~4. see section 1.5 on page 24 for signal descriptions. note: default output is display enable (de). the current drive capability of this pin may be set high or low via designated registers in the host interfac e. by default, the current drive will be low. this signal will be high impedance when vid_std[5:0] = 00h. 45 lvds/pclk3_vdd ? power supply most positive power supply connecti on for pclk3 output circuitry and lvds driver. connect to +1.8v dc. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 16 of 95 46, 47 pclk3 , pclk3 ? output clock signal outputs signal levels are lvds compatible. differential video clock output signal. pclk3 / pclk3 present a differential video sample rate clock output to the application layer. by default, after system reset, this output will operate at the fundamental frequency determined by the setting of the vid_std[5:0] pins. it is possible to define other non-standard fundamental clock rates using the host interface. it is also possible to select di fferent division ratios for the pclk3 / pclk3 outputs by programming designated registers in the host interface. a clock output of the fundamental rate, fundamental rate 2, or fundamental rate 4 may be selected. the pclk3 / pclk3 outputs will be high impedance when vid_std[5:0] = 00h. 48 lvds/pclk3_gnd ? power supply ground connection for pclk3 output ci rcuitry and lvds driver. connect to gnd. 49 pclk2 ? output clock signal output signal levels are lvcmos/lvttl compatible. video clock output signal. pclk2 presents a video sample rate clock output to the application layer. by default, after system reset, the pclk2 output pin will operate at the fundamental frequency determined by the setting of the vid_std[5:0] pins. it is possible to define other non-standard fundamental clock rates using the host interface. it is also possible to select different division ratios for the pclk2 output by programming designated registers in the host interface. a clock output of the fundamental rate, fundamental rate 2, or fundamental rate 4 may be selected. by setting designated registers in the host interface, the current drive capability of this pin may be set high or low. by default, the current drive will be low. the pclk2 output will be held low when vid_std[5:0] = 00h. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 17 of 95 51 pclk1 ? output clock signal output signal levels are lvcmos/lvttl compatible. video clock output signal. pclk1 presents a video sample rate clock output to the application layer. by default, after system reset, the pclk1 output pin will operate at the fundamental frequency determined by the setting of the vid_std[5:0] pins. it is possible to define other non-standard fundamental clock rates using the host interface. it is also possible to select different division ratios for the pclk1 output by programming designated registers in the host interface. a clock output of the fundamental rate, fundamental rate 2, or fundamental rate 4 may be selected. by setting designated registers in the host interface, the current drive capability of this pin may be set high or low. by default, the current drive will be low. the pclk1 output will be held low when vid_std[5:0] = 00h. 52 pclk1&2_gnd ? power supply ground connection for pclk1&2 ci rcuitry. connect to gnd. 53 pclk1&2_vdd ? power supply most positive power supply connection for pclk1&2 circuitry. connect to +1.8v dc. 54 phs_vdd ? power supply most positive power supply connection for the video clock phase shift internal block. connect to +1.8v dc. 55 phs_gnd ? power supply ground connection for the video clock phas e shift internal block. connect to gnd. 56 jtag/host non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sclk_tclk, sdout_tdo, and sdin_tdi are configured for jtag boundary scan testing. when set low, cs _tms, sclk_tclk, sdout_tdo, and sdin_tdi are configured as gspi pins fo r normal host interface operation. 57 sclk_tclk non synchronous input signal input signal levels are lvcmos/lvttl compatible. serial data clock / test clock. all jtag / host interface address and data are shifted into/out of the device synchronously with this clock. host mode (jtag/host = low): sclk_tclk operates as the host interface serial data clock, sclk. jtag test mode (jtag/host = high): sclk_tclk operates as the jtag test clock, tclk. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 18 of 95 58 sdin_tdi synchronous with sclk_tclk input signal input signal levels are lvcmos/lvttl compatible. serial data input / test data input. host mode (jtag/host = low): sdin_tdi operates as the host interf ace serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high): sdin_tdi operates as the jtag test data input, tdi. 59 sdout_tdo synchronous with sclk_tclk output signal input signal levels are lvcmos/lvttl compatible. serial data output / test data output. host mode (jtag/host = low): sdout_tdo operates as the host interface serial output, sdout, used to read status and configuration informat ion from the internal registers of the device. jtag test mode (jtag/host = high): sdout_tdo operates as the jtag test data output, tdo. 60 cs _tms synchronous with sclk_tclk input signal input signal levels are lvcmos/lvttl compatible. chip select / test mode select. host mode (jtag/host = low): cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high): cs _tms operates as the jtag test mode select, tms, and is active high. 61 reset non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to reset the internal operating c onditions to their default settings or to reset the jtag test sequence. host mode (jtag/host = low): when asserted low, all host registers and functional blocks will be set to their default conditions. all i nput and output signals will become high impedance, except pclk1 and pclk2, which will be set low. when set high, normal operation of the device will resume. the user must hold this pin low during power-up and for a minimum of 500 us after the last supply has reached its operating voltage. jtag test mode (jtag/host = high): when asserted low, all host registers and functional blocks will be set to their default conditions and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence will resume. table 1-1: pin descriptions (continued) pin number name timing type description
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 19 of 95 figure 1-1: xtal1 and xtal2 reference circuits 64 genlock non synchronous input control signal input signal levels are lvcmos/lvttl compatible. selects genlock mode or free run mode. when this pin is set low and the dev ice has successfully genlocked the output to the input reference, the device will enter genlock mode. the video clock and timing outputs will be frequency and phase locked to the detected reference signal. when this pin is set high, the video clock and the reference-timing generator will free-run. by default, the gs4901b?s audio cl ocks will be genlocked to the output video clock regardless of the setting of this pin. note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the gener ated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. ? ground pad ? ? ground pad on bottom of package must be soldered to main ground plane of pcb. table 1-1: pin descriptions (continued) pin number name timing type description x1 38pf x2 24pf 1m 6 7 x1 x2 6 7 nc external clock external crystal connection external clock source connection notes: 1. capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2. x1 serves as an input, which may alternatively accept a 27mhz clock source. to accomodate this, mismatched capacitor values are recommended.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 20 of 95 1.4 pre-programmed recognized video standards table 1-2 describes the video standards recognized by the gs4901b/GS4900B. the device will automatically recognize vid_st d[5:0] = 1 to 10. in order to enable the device to recognize and lock to any of the hd reference formats defined by vid_std[5:0] = 11 to 38, the user must set the corresponding bit low in the reference_standard_disable register, located at address 11h-13h of the host interface. in addition, the user must se t the hd_reference_enable bit of register 82h[7] high. please see the descriptions of the reference_standard_disable and hd_reference_enable registers in section 3.10.3 on page 66 . if an hd reference format is left disabled in the reference_standard_disable register, or if the hd_reference_enable bit is not set high in register 82h, the device will not recognize this format should it be applied to the input of the device. the user may select vid_std[5:0] = 1 or 3-10 only as output formats. if desired, the external vid_std[5:0] pins may be ignored by setting bit 1 of the video_control register, and the video standard may instead be selected via the vid_std[5:0] register of the host interface (see section 3.10.3 on page 66 ). although the external vid_st d[5:0] pins will be ignored in this case, they should not be left floating. note: vid_std[5:4] should always be set low by the application layer since these pins are not required to select output video standards 1 to 10.
37703 - 0 april 2006 21 of 95 gs4901b/GS4900B prelim inary data sheet table 1-2: recognized video standards vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / total line total lines / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard 0 pclk1&2 =low. pclk3/pclk3 = high impedance ?????????? 1 4fsc 525 / 2:1 interlace 14.32 910 525 768 67 negative 3 negative 486 smpte 244m 2* composite pal 625 / 2:1 interlace / 25 ? ? 625 ? ? negative 2.5 negative 576 ? 3 601 525 / 2:1 interlace 27 1716 525 1440 127 negative 3 negative 486 smpte 125m/267m 4? 601 625 / 2:1 interlace 27 1728 625 1440 127 negative 2.5 negative 576 itu-r bt.601-5 5 601 ? 18mhz 525 / 2:1 interlace 36 2288 525 1920 169 negative 3 negative 486 smpte 267m 6? 601 ? 18 mhz 625 / 2:1 interlace 36 2304 625 1920 169 negative 2.5 negative 576 itu-r bt.601-5 7 720x486/59.94/2:1 interlace 54 3432 525 2880 252 negative 3 negative 486 smpte rp174 / smpte 347m 8? 720x576/50/2:1 interlace 54 3456 625 2880 252 negative 2.5 negative 576 itu-r bt.799 / smpte 347m 9 720x483/59.94/1:1 progressive 54 1716 525 1440 127 negative 6 negative 483 smpte 293m / smpte 347m 10 720x576/50/1:1 progressive 54 1728 625 1440 127 negative 5 negative 576 itu-r bt.1358 / smpte 347m 11* 1280x720/60/1:1 progressive 74.25 1650 750 1280 80 tri 5 negative 720 smpte 296m 12* 1280x720/59.94/1:1 progressive 74.175 1650 750 1280 80 tri 5 negative 720 smpte 296m 13* 1280/720/50/1:1 progressive 74.25 1980 750 1280 80 tri 5 negative 720 smpte 296m
37703 - 0 april 2006 22 of 95 gs4901b/GS4900B prelim inary data sheet 14* 1280x720/30/1:1 progressive 74.25 3300 750 1280 80 tri 5 negative 720 smpte 296m 15* 1280x720/29.97/1:1 progressive 74.175 3300 750 1280 80 tri 5 negative 720 smpte 296m 16* 1280x720/25/1:1 progressive 74.25 3960 750 1280 80 tri 5 negative 720 smpte 296m 17* 1280x720/24/1:1 progressive 74.25 4125 750 1280 80 tri 5 negative 720 smpte 296m 18* 1280x720/23.98/1:1 progressive 74.175 4125 750 1280 80 tri 5 negative 720 smpte 296m 19* 1920x1035/60/2:1 interlace 74.25 2200 1125 1920 80 tri 5 negative 1035 smpte 260m 20* 1920x1035/59.94/2:1 interlace 74.175 2200 1125 1920 80 tri 5 negative 1035 smpte 260m 21* 1920x1080/60/1:1 progressive 148.5 2200 1125 1920 80 tri 5 negative 1080 smpte 274m 22* 1920x1080/59.94/1:1 progressive 148.35 2200 1125 1920 80 tri 5 negative 1080 smpte 274m 23* 1920x1080/50/1:1 progressive 148.5 2640 1125 1920 80 tri 5 negative 1080 smpte 274m 24* reserved ? ? ? ? ? ? ? ? ? ? 25* 1920x1080/60/2:1 interlace 74.25 2200 1125 1920 80 tri 5 negative 1080 smpte 274m 26* 1920x1080/59.94/2:1 interlace 74.175 2200 1125 1920 80 tri 5 negative 1080 smpte 274m 27* 1920x1080/50/2:1 interlace 74.25 2640 1125 1920 80 tri 5 negative 1080 smpte 274m 28* reserved ? ? ? ? ? ? ? ? ? ? table 1-2: recognized video standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / total line total lines / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard
37703 - 0 april 2006 23 of 95 gs4901b/GS4900B prelim inary data sheet 29* 1920x1080/30/1:1 progressive 74.25 2200 1125 1920 80 tri 5 negative 1080 smpte 274m 30* 1920x1080/30/psf 74.25 2200 1125 1920 80 tri 5 negative 1080 smpte rp 211 31* 1920x1080/29.97/1:1 progressive 74.175 2200 1125 1920 80 tri 5 negative 1080 smpte 274m 32* 1920x1080/29.97/psf 74.175 2200 1125 1920 80 tri 5 negative 1080 smpte rp 211 33* 1920x1080/25/1:1 progressive 74.25 2640 1125 1920 80 tri 5 negative 1080 smpte 274m 34* 1920x1080/25/psf 74.25 2640 1125 1920 80 tri 5 negative 1080 smpte rp 211 35* 1920x1080/24/1:1 progressive 74.25 2750 1125 1920 80 tri 5 negative 1080 smpte 274m 36* 1920x1080/24/psf 74.25 2750 1125 1920 80 tri 5 negative 1080 smpte rp 211 37* 1920x1080/23.98/1:1 progressive 74.175 2750 1125 1920 80 tri 5 negative 1080 smpte 274m 38* 1920x1080/23.98/psf 74.175 2750 1125 1920 80 tri 5 negative 1080 smpte rp 211 * vid_std[5:0] = 2 and 11-38 are recognized as input references only. in addition, vid_std[5:0] = 11-38 must be enabled in the reference_standard_disable register and the hd_reference_enable bit of register 82h[7] must be se t high before they will be recognized by the device. ? when vid_std = 4, 6, or 8, the vblanking output pulse width is 2 lines too long for field 1 and 1 line too short for field 2 when compared to the digital timing defined in itu-r bt.656 and itu-r bt.799. table 1-2: recognized video standards (continued) vid_std [5:0] system nomenclature video pclk frequency (mhz) pclks / total line total lines / frame pclks / active line h sync width (clocks) h sync polarity v sync width (lines) v sync polarity active lines / frame scan format standard
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 24 of 95 1.5 output timing signals table 1-3 describes the output timing signal s available to the user via pins timing_out_1 to ti ming_out_8. the user may outpu t any of the signals listed below on each pin by programming the output_select registers beginning at address 43h of the host interface. table 1-3: output timing signals signal name description default output pin h sync the h sync signal has a leading edge at the start of the horizontal sync pulse. its width is determined by the selected video standard (see table 1-2 ). in genlock mode the leading edge of the output h sync signal is nominally simultaneous with the half amplitude point of the reference hsync input. this timing may be offset using the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). by default, after system reset, the polar ity of the h sync signal output will be active low. the polarity may be selected as active high by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). timing_out_1 h blanking the h blanking signal is used to indicate the portion of the video line not containing active video data. the h blanking signal will be low (default polarity) for the portion of the video line containing valid video samples. the signal will be low at the first valid pixel of the line, and high after t he last valid pixel of the line. the h blanking signal remains high thro ughout the horizontal blanking period. the width of this signal will be dete rmined by the selected video standard (see table 1-2 ). when in genlock mode, the output h blank ing signal will be phase locked to the reference hsync input. this timing may be offset using the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). timing_out_2 v sync the v sync timing signal has a leading edge at the star t of the vertical sync pulse. its width is determined by the selected video standard (see table 1-2 ). the leading edge of v sync is nomina lly simultaneous with the leading edge of the first broad pulse. when in genlock mode, the output v sy nc signal will be phase locked to the reference vsync input. this timing may be offset using the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). by default, after system reset, the polarit y of the v sync signal output will be active low. the polarity may be selected as active high by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). timing_out_3
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 25 of 95 v blanking the v blanking signal is used to indicate the portion of the video field/frame not containing active video lines. the v blanking signal will be low (default polarity) for the portion of the field/frame containing valid video data, and will be high throughout the vertical blanking period. the width of this signal will be dete rmined by the selected video standard (see table 1-2 ). when in genlock mode, the output v blankin g signal will be phase locked to the reference vsync input. this timing may be offset using the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). note: when vid_std = 4, 6, or 8, the vblanking output pulse width is 2 lines too long for field 1 and 1 line too short for field 2 when compared to the digital timing defined in itu-r bt.656 and itu-r bt.799. timing_out_4 f sync the f sync signal is us ed to indicate field 1 and field 2 for interlaced video formats. the f sync signal will be high (default polar ity) for the entire period of field 1. it will be low for all lines in field 2 and fo r all lines in progressive scan systems. the width and timing of this signal will be determined by the v sync parameters of the selected video standard (see table 1-2 ). the f sync signal always changes state on the leading edge of v sync. when in genlock mode, the output f sync signal will be phase locked to the reference fsync input. this timing may be offset using the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). timing_out_5 f digital f digital is used in digital inte rlaced standards to indicate field 1 and field 2. the f digital changes state at the leadi ng edge of every v blanking pulse. it will be low (default polarity) for the entire period of field 1 and for all lines in progressive scan systems. it will be high for all lines in field 2 . the width and timing of th is signal will be determined by the timing parameters of the selected video standard (see table 1-2 ). when in genlock mode, the output f digi tal signal will be phase locked to the reference fsync input. this timing may be offset using the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). timing_out_6 table 1-3: output timing signals (continued) signal name description default output pin
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 26 of 95 10 field identification the 10 field identification ( 10fid) signal is used to indicate the 10-field sequence for 29.97hz, 30hz, 59.94hz and 60hz video standards. it will be low for output standards with other frame rates. the sequence defines the phase relations hip between film frames and video frames, so that cadence may be maintained in mixed format environments. the 10fid signal will be high (default polarity) for one line at the start of the 10-field sequence. it will be low for al l other lines. the signal?s rising and falling edges will be simultaneous with the leading edge of the h sync output signal. alternatively, by setting bit 4 of the video_control register (see section 3.10.3 on page 66 ), the 10fid output signal may be configured to go high (default polarity) on the leading edge of the h sync output on line 1 of the first field in the 10 field sequence, and be reset low on the leading edge of the h sync pulse of the first line of the se cond field in the 10 field sequence. when in genlock mode, the output 10 fid signal will be phase locked to the 10fid reference input. if a 10fid input is not provided to the device, the user must configure the 10fid output using r egister 1ah of the host interface (see section 3.8.1 on page 57 ). for applications involving audio, this signal may be used in place of the afs signal if the format selected is appropriate for a 10 field afs repetition rate, and the desired phase relationship of audio to video clock phasing coincides with the desired film frame cadence. the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). please see section 3.8.1 on page 57 for more detail on the 10fid output signal. timing_out_7 display enable the display enable (de) signal is used to indicate the display enable for graphic display interfaces. this signal will be high (default polari ty) whenever pixel information is to be displayed on the display device (i.e. whenever both h blanking and v blanking are in the active video state) the width and timing of th is signal will be determined by the timing parameters of the selected video standard (see table 1-2 ). the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 on page 66 ). timing_out_8 audio frame sync (gs4901b only) the audio frame sync (afs) signal is high (default polarity) for the duration of the first line of the n?th video frame to indicate that the aclk dividers are reset at the start of line 1 of that frame. it is defined according to the frame rate of the video format and the selected audio sample rate programmed via the vid_std[5:0] and asr_sel[2:0] pins or the host interface. for example, if the video format is based on a 59.94hz frame rate and the audio sample rate clock is 48khz, then n= 5, and the afs signal will be identical to the 10fid signal. by default, the afs signal is reset by the 10 field identification (10fid) reference input. this feature may be dis abled using the audio_control register at address 31h of the host interface (see section 3.10.3 on page 66 ). the afs signal may also be reset using register 1ah of the host interface. with no reference, the frame divide by ?n? contro lling the afs signal will free-run at an arbitrary phase. the default polarity of this signal may be inverted by programming the polarity register at address 56h of the host interface (see section 3.10.3 ). please see section 3.8.2 on page 58 for more detail on the afs output signal. ? table 1-3: output timing signals (continued) signal name description default output pin
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 27 of 95 user_1~4 the gs4901b/GS4900B offers four us er programmable output signals. each user signal is controlled by four timing registers and a polarity select bit. the timing registers define the start and stop times in h pixels and v lines and begin at address 57h of the host interface (see section 3.10.3 on page 66 ). each user signal is indi vidually programmable and the polarity, position, and width of each output may be defined with respect to the h, v, and f output timings of the device. each output signal may be programmed in both the horizontal and vertical di mensions relative to the leading edges of h and v sync. if desired, the pulses produced ma y then be combined with a logical and, or, or xor function to produce a composite signal (for example, a horizontal back porch pulse during active li nes only, or the active part of lines 15 through 20 for vertical information retrieval). each output has selectable polarity. please see section 3.8.3 on page 59 for more detail on the user_1~4 output signals. ? table 1-3: output timing signals (continued) signal name description default output pin
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 28 of 95 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter conditions value/units supply voltage core and analog (core_vdd, vid_pll_vdd, aud_pll_vdd, phs_vdd, analog_vdd) ? -0.3v to +2.1v supply voltage i/o (io_vdd, xtal_vdd) ? -0.3v to +3.6v input voltage range (any input) io_vdd = +3.3v -0.3v to +5.5v io_vdd = +1.8v -0.3v to +3.6v operating temperature ? -20c < t a < 85c storage temperature ? -50c < t stg < 125c soldering temperature ? 260c esd protection on all pins ? 1 kv table 2-1: dc electrical characteristics v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes system operating temperature range t a ? 0 25 70 c 1 core power supply voltage core_vdd ? 1.71 1.8 1.89 v ? digital i/o buffer power supply voltage io_vdd 1.8v operation 1.71 1.8 1.89 v ? io_vdd 3.3v operation 3.135 3.3 3.465 v ? video pll power supply voltage vid_pll_vdd ? 1.71 1.8 1.89 v ? audio pll power supply voltage (gs4901b only) aud_pll_vdd ? 1.71 1.8 1.89 v ? analog power supply voltage analog_vdd ? 1.71 1.8 1.89 v ? crystal buffer power supply voltage xtal_vdd 1.8v operation 1.71 1.8 1.89 v ? xtal_vdd 3.3v operation 3.135 3.3 3.465 v ? video clock phase shift supply voltage phs_vdd ? 1.71 1.8 1.89 v ?
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 29 of 95 system power p d gs4901b core_vdd = max io_vdd = max t = 70 o c unloaded, max pclk frequency ??415mw? p d gs4901b core_vdd = 1.8v io_vdd = 3.3v t = 25 o c unloaded, pclk = 27 mhz ?265?mw? p d GS4900B core_vdd = max io_vdd = max t = 70 o c unloaded, max pclk frequency ??365mw? p d GS4900B core_vdd = 1.8v io_vdd = 3.3v t = 25 o c unloaded pclk = 27 mhz ?215?mw? digital i/o input voltage, logic low v il 1.8v operation ? ? 0.35 x vdd v? v il 3.3v operation ? ? 0.8 v ? input voltage, logic high v ih 1.8v operation 0.65 x io_vdd ?3.6v ? v ih 3.3v operation 2.145 ? 5.25 v ? output voltage, logic low v ol current drive = high or low as selected ??0.4v2 output voltage, logic high v oh current drive = high or low as selected 0.65 x io_vdd ??v 2 digital output currents timing output drive current ? io_vdd = 1.8v current drive = low ?5?ma? ? io_vdd = 3.3v current drive = low ?10?ma? ? io_vdd = 1.8v current drive = high ?7?ma? ? io_vdd = 3.3v current drive = high ?12?ma? table 2-1: dc electrical characteristics (continued) v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 30 of 95 2.3 ac electrical characteristics clock output drive current ? io_vdd = 1.8v current drive = low ?5?ma? ? io_vdd = 3.3v current drive = low ?7?ma? ? io_vdd = 1.8v current drive = high ?7?ma? ? io_vdd = 3.3v current drive = high ?10?ma? output voltage lvds, common mode v ocm ? 1.125 1.25 1.375 v 3 output voltage lvds, differential v odiff ??350?mv3 lvds high-impedance leakage current ? to 1.8v or gnd ? ? 1.4 ua ? notes 1. all dc and ac electrical para meters within specification. 2. assuming that the current being sourced or sinked is less than the timing output drive current specified. 3. into a 100 termination connected between pclk3 and pclk3 . table 2-1: dc electrical characteristics (continued) v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes table 2-2: ac electrical characteristics v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes system reference detection time ? from when the reference input is first present ?24frames? digital i/o pclk output frequency ? ? 3.375 ? 54 mhz ? pclk jitter ? xtal_vdd = 3.3v ? 300 ? ps 1, 2 pclk duty cycle ? ? 40 ? 60 % ? pclk1 & pclk2 rise/fall times 15pf load 20% - 80% ? io_vdd = 1.8v current drive = low ??1.7ns? ? io_vdd = 3.3v current drive = low ??1.5ns? ? io_vdd = 1.8v current drive = high ??1.1ns? ? io_vdd = 3.3v current drive = high ??0.9ns?
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 31 of 95 pclk3 rise/fall time 20% - 80% ? 100 differential load 10pf to ground per pin ? ? 850 ps ? pclk outputs relative timing skew ? default pclk phase delay of zero -3 ? 3 ns 3 aclk frequency (gs4901b only) ? ? 0.0097 ? 49.152 mhz ? aclk duty cycle (gs4901b only) ? ? 40?60%4 aclk1-3 rise/fall times 15pf load 20% - 80% (gs4901b only) ? io_vdd = 1.8v current drive = low ??3.0ns? ? io_vdd = 3.3v current drive = low ??1.5ns? ? io_vdd = 1.8v current drive = high ??2.5ns? ? io_vdd = 3.3v current drive = high ??1.4ns? aclk outputs relative timing skew (gs4901b only) ?? -3?3ns3 digital timing output delay time t od ???4.3ns5 digital timing output hold time t oh ? 1??ns5 digital timing output rise/fall times 15pf load 20% - 80% ? io_vdd = 1.8v current drive = low ??3.0ns? ? io_vdd = 3.3v current drive = low ??1.5ns? ? io_vdd = 1.8v current drive = high ??2.5ns? ? io_vdd = 3.3v current drive = high ??1.4ns? gspi gspi input clock frequency f gspi ? ? ? 10.0 mhz 6 gspi clock duty cycle dc gspi ? 40?60%6 gspi input setup time t 3 in figure 3-15 ?1.5??ns6 table 2-2: ac electrical characteristics (continued) v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 32 of 95 figure 2-1: pclk to timing _out signal output timing gspi input hold time t 8 in figure 3-15 ?1.5??ns6 notes 1. the video output clock may be directly connected to gennum?s gs 9062 serializer for a smpte-compliant sdi output with output j itter below 0.2ui. 2. all output standards except vid_std[5:0] = 1 (450ps typ.) and vid_std[5:0] = 5 or 6 (500ps typ.) 3. timings from any clk output to any other clk output. 4. if fs=96khz and aclk is configured to output a clock signal at 192fs or 384fs, a 512fs clock will typica lly have a 33% duty c ycle distortion. see section 3.7.2 on page 53 . 5. with pclk phasing delay set to nominal (zero offset), each increment of the clock phasing adj ustment decreases output hold ti me and delay time by a nominal 700ps. the times t od and t oh are defined in figure 2-1 . 6. for detailed gspi timing parameters, please refer to table 3-12 . table 2-2: ac electrical characteristics (continued) v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes table 2-3: suggested extern al crystal specification 27.000000 mhz at cut nominal dissipation = 50 uw frequency accuracy at 25c = +/- 10ppm frequency variation 0-70c = +/- 10ppm asr = 50 +/- 20 note: the user may select an appropriate crystal accuracy for their application. if the device is operating in free run mode, the output clock and timing signals will have the same accuracy as the crystal. however, if operating in genlock mode, all output signals are based on the input reference, and therefore a less accurate crystal may be sufficient. see section 3.2 on page 34 . 50% t oh t od v oh v ol v oh v ol timing_out pclk
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 33 of 95 2.4 solder reflow profiles the device is manufactured with matte-sn te rminations and is compatible with both standard eutectic and pb-free solder re flow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 2-2 . the recommended standard pb reflow profile is shown in figure 2-3 . figure 2-2: maximum pb-free solder reflow profile (preferred) figure 2-3: standard pb solder reflow profile 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 34 of 95 3. detailed description 3.1 functional overview the gs4901b/GS4900B is a highly flexib le, digitally controlled clock synthesis circuit and timing generator with g enlock capability. the device has two main modes of operation: genlock mode and free run mode. in genlock mode, the video clock and timi ng outputs, will be frequency and phase locked to the detected reference input signal. in free run mode, the occurrence of all frequencies is based on a 27mhz external crystal reference. the gs4901b/GS4900B will re cognize input reference si gnals conforming to 36 different video standards. it supports cros s-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. when the device is in genlock mode a nd the input reference is removed, the gs4901b/GS4900B will enter fr eeze mode. in this mo de, the output clock and timing signals will maintain their previo usly genlocked phas e and frequency to within +/- 2ppm. the user may select to output one of 4 different video sample clock rates. the chosen clock frequency may be further internally divided, and is available on two video clock outputs and one lvds video cl ock output pair. the video clocks may also be individually phase delayed with respect to the timing outputs for clock skew control. eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 9 different video formats: hsync, hblanking, vsync, vblanking, f sync, f digital, afs (gs4901b only), de, and 10fid. in addition, the gs4901b provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7khz to 96khz. audio to video phasing is accomplished by either an external 10fid input reference, a 10fid signal specified via internal regi sters, or a user-programmed audio frame sequence. 3.2 modes of operation the gs4901b/GS4900B will operate in eith er genlock mode or free run mode depending on the setting of the genlock pin. these two modes are described in section 3.2.1 on page 35 and section 3.2.2 on page 38 respectively. if desired, the external genlock pin may be ignored by setting bit 5 of the genlock_control register (address 16h) so that genlock can instead be controlled via the host interface (see section 3.10.3 on page 66 ). although the external genlock pin will be ignored in this case , it should not be left floating.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 35 of 95 3.2.1 genlock mode when the application layer sets the genlock pin low and the device has successfully genlocked the outputs to th e input reference, the gs4901b/GS4900B will enter genlock mode. in th is mode, all clock and timi ng generator outputs will be frequency and phase locked to the detected input reference signal. the pclk outputs will be locked to the h reference. when in genlock mode, the output clock and timing signals are generated using the applied reference signal. the 27mhz crystal reference is necessary for operation; however, neither crystal accura cy nor changes in crystal frequency (due to a shift in operating temp erature) will affect the output signals. for example, the output signals will be gener ated with the same accu racy whether the 27mhz reference crystal has an accuracy of 10ppm or 100ppm. the gs4901b/GS4900B supports cross-lo cking, allowing the outputs to be genlocked to an incoming reference that is different from the output video standard selected (see section 3.6 on page 46 ). note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the generated clock and timing ou tputs of the device may correspond to the internal default settings of the chip until a reference is applied. 3.2.1.1 genlock timing offset by default, the phase of the clock and ti ming out signals is genlocked to the input reference signal. these output signals may be phase adjusted with respect to the input reference by programmi ng the host interface (see section 3.10.3 on page 66 ). offsets are separately programmable in terms of clock phase, horizontal phase, and vertical phase (i.e. frac tions of a pixel, pixels, and lines). genlock timing offsets can be used to co -time the output of a piece of equipment containing the gs4901b/GS4900B with the out puts of other equipment at different locations. the signal leaving the piece of equipment containing the gs4901b/GS4900B may pass through processing equipment with significant fixed delays before arriving at the switcher. th ese delays may include video line delays or even field delays. to compensate for these delays, genlock timing offsets allow the user to back-time the output of the equipment relative to the input reference. using the host interface, the following registers may be programmed once the device is stably locked: ? clock_phase_offset (1dh) - with a range of zero to one clock pulse in increments of between 1/128 and 1/512 of a clock period (depending on the pclk frequency). the incr ements will be between 100ps and 150ps. all clock and timing output signals will be de layed by the clock phase offset programmed in this register. ? h_offset (1bh) - the difference between the reference hsync signal and the output h sync and/or h blanking signal in clock pulses, with a control range of zero to +1 line. all timing output signal s will be delayed by the horizontal offset programmed in this register.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 36 of 95 ? v_offset (1ch) - the difference between the reference vsync signal and the output v sync and/or v blanking in lines , with a control range of zero to +1 frame. all line-based timing output signals will be delayed by the vertical offset programmed in this register. the encoding scheme for the clock_phase_offset register (1dh) is shown in table 3-1 . the offset programmed will be in the po sitive direction. note that the step size will depend on the frequency of th e output video clock. the value programmed in the h_offset register (1bh) must not exceed the maximum number of clock periods per line of the outgoing video standard. similarly, the value programmed in the v_ offset register (1ch) must not exceed the maximum number of lines per frame of the outgoing standard. both horizontal and vertical offsets will be in the positive direction. negative offsets (advances) are achieved by programming a value in the app ropriate register equal to the maximum allowable offset minus the desired advance. notes: 1. the device will delay all output timing si gnals by 2 pclks relative to the input hsync reference. this will occur even when the h_offset register is not programmed. the user may compensate fo r this delay by subtracting 2 pclk cycles from the desired horizontal offset before loading the value into the host interface. 2. for both sync and blanking-based input references, the devi ce will advance all line-based output timing signals by 1 line relative to the input vsync reference for all output stan dards except vid_std[5:0] = 4, 6, and 8. this will occur even when the v_offset regist er is not programmed. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. table 3-1: clock_phase_offs et[15:0] encoding scheme vid_std[5:0] setting output video clock frequency step size (fraction of a pclk) maximum number of steps bits required to set the number of steps clock_phase_offset [15:0] settings 1f pclk < 20mhz 511 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 8 000001b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 3-6 20mhz < f pclk < 40mhz 255 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 000010b 7 b 6 b 5 b 4 0b 3 b 2 b 1 b 0 7-10 40mhz < f pclk < 54mhz 127 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 6 000100b 6 b 5 b 4 00b 3 b 2 b 1 b 0 note: program clock_phase_offset = 0000 0000 0000 0000b to achieve a zero clock phase offset. 1 512 -------- - 1 256 -------- - 1 128 -------- -
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 37 of 95 3. when locking the 525-line sd output standards to the ?f/1.001? hd input reference standards, the device will delay all line-based output timing signals by vsync lines relative to the input vsync reference. this will occur even when the v_offset register is not programmed. the user may compensate for this delay by subtracting vsync lines from the desire d vertical offset before loading this value into the register. the value vsync is given by the equation: where: hsync_in_period = the period of the h reference pulse vsync_hsync = the time difference be tween the leading edges of the applied v and h reference pulses hsync_out_period = the period of the generated h sync output see figure 3-1 . h_feedback_divide represents the numerator of the ratio of the output clock frequency to the frequency of the h reference pulse. figure 3-1: sd-hd calculation 4. for sync-based input refe rences, the device will ad vance all line-based output timing signals by 1 line if the value pr ogrammed in the h_offset register is greater than 20. the user may compensate for this advance by adding 1 line to the desired vertical offset before lo ading this value into the register. in addition, the internal v_lock and f_lock signals reported in bits 3 and 4 of register 16h will be low when h_offset = 21 only, although the device will remained genlocked. the user may choose to mask these lock signals such that the device will continue to re port genlock under this condition. vsync hsync_in_period vsync _hsync 2 ( hsync_out_period ) ? + = hsync vsync h sync v sync vsync_hsync hsync_out_period hsync_in_period vsync
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 38 of 95 5. for blanking-based input references, the device will advance all line-based output timing signals by 1 line if the va lue programmed in the h_offset register is greater than the number of output video clock cycles from the start of h sync to the end of active video (hsync_to_eav) + 20. the value of hsync_to_eav is reported in register 51h and changes according to the output vid_std selected. the user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value in to the register. in addition, the internal v_lock and f_lock signals reported in bits 3 and 4 of register 16h will be low when h_offset = hsync_to_eav + 21 only, although the device will remained genlocked. the user may choose to mask these lock signals such that the device will c ontinue to report g enlock under this condition. 6. the offsets that occur as described in notes 1-5 are independent of one another and must be accounted for as such. 3.2.1.2 freeze mode when the device is in genlock mode a nd the input reference is removed, the gs4901b/GS4900B will enter fr eeze mode. the behaviou r of the device during loss and re-acquisition of an input reference signal is described in section 3.5.3 on page 44 . in freeze mode, the frequency of the output cloc k and timing signals will be maintained to within +/- 2ppm. this assumes a loop bandwidth of 10hz. also, if the frequency of the 27mhz reference crysta l shifts while in freeze mode, the frequency of the output clock and timing signals will shift as well. 3.2.2 free run mode the gs4901b/GS4900B will enter fr ee run mode when the genlock pin is set high by the application laye r. in this mode, the occurr ence of all frequencies is based on the external 27mhz reference input. therefore, the frequency of the output clock and timing si gnals will have the same accuracy as the crystal reference. if operating in free run mode, using a more accurate crystal (e.g. 10ppm) ensures more accurate clock and timing signals are generated. note: in free run mode, the audio clocks of the gs4901b will remain genlocked to the video clock. figure 3-2 summarizes the differences in ou tput accuracy in each mode of operation. assuming a crystal reference of +/-100ppm, in free run mode the frequency of the output clock and timing signals will be as accurate as the crystal. in genlock mode the frequency will be as accurate as th e input reference regardless of the crystal accuracy. in freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 39 of 95 figure 3-2: output accuracy and modes of operation 3.3 output timing format selection at device power-up (described in section 3.12 on page 88 ), the application layer should immediately set the external vi d_std[5:0] and asr_sel[2:0] pins. the vid_std[5:0] pins are used to select a pre-programmed output video format. the asr_sel[2:0] pins are only available on the gs4901b, and are used to select the fundamental audio frequency or to turn off audio clock generation. the output timing formats selectable by the user via the vid_std[5:0] pins are listed in section 1.4 on page 20 . table 3-7 in section 3.7.2 on page 53 lists the audio sample rates available via the asr_sel[2:0] pins. note: the vid_std[5:4] pins should be grounded by the application layer since these pins are not required to select output video standards 1 to 10. on power-up, the device will first check the status of the genlock pin. if genlock is set low and a valid reference has been applied to the inputs, the device will output the sele cted video standard while attempting to genlock. however, if a reference signal has not been applied and genlock =low, the initial clock and timing outputs may be det ermined by the internal default settings of the chip. if genlock is set high, the device will immediately enter free run mode and will correctly output the select ed video standard. when operating in free run or genlock mode, the gs4901b/GS4900B will continuously monitor the settings of the vid_std[5:0] and asr_sel[2:0] pins. if the user wishes to change t he format of the output clo cks and timing signals, these pins may be reconfigured at any time, al though it is recommended that the device be reset when changing output video standards. free run genlock freeze 27 mhz -2ppm no input reference reference applied reference lost time assumption: reference xtal is 27mhz+/-100ppm -100ppm +100ppm +2ppm + notes: 1. t represents the temperature variability of the crystal 2. diagram not to scale. t t - t + t - t
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 40 of 95 3.4 input reference signals the hsync, vsync, fsync, and 10fid reference signals are applied to the gs4901b/GS4900B via the designated input pins. to operate in genlock mode, the input reference signals must be valid and must conform to a recognized video standard (see section 3.5 on page 42 ). in free run mode, no input reference is required. section 3.4.1 on page 40 describes the hsync, vsyn c and fsync in put timing. the 10fid input signal is discussed in section 3.4.2 on page 41 . 3.4.1 hsync, vsync, and fsync the hsync, vsync, and fsync input reference signals may have analog timing, such as from gennum?s gs4981/82 sync separators ( figure 3-3 ), or may have digital timing, such as from gennum?s gs1559/60a/61 deserializers ( figure 3-4 ). section 1.4 on page 20 lists the 36 pre-programmed video timing formats recognized by the gs4901b/GS4900B. if the input reference format does not in clude an f sync signal, the fsync pin should be held low. figure 3-3: example hsync, vsync, an d fsync analog input timing from a sync separator figure 3-4: example h blanking, v blanking , and f digital input timing from an sdi deserializer hsync vsync fsync h:v:f timing - hd 20-bit output mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff 000 000 3ff v f 000 000 3ff 000 000 3ff xyz (eav) xyz (sav) xyz (sav) h signal timing typical h timing alternative h timing
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 41 of 95 3.4.2 10fid the 10fid input is a reset pin, which can be used to reset the divider for the 10fid output signal. in th e gs4901b, the 10fid input pin will also reset the divider for the afs output signal. this default setting may be modified using the audio_control register of the host interface (see section 3.10.3 on page 66 ). the gs4901b will reset the phase of the aud io clocks to the leading edge of the h sync output on line 1 of every output frame in which the 10fid input is high. if the input reference format does not incl ude a 10 field id signal, the external 10fid input pin should be held low. the timing of the 10fid input signal is shown in figure 3-5 . figure 3-5: 10fid input timing 3.4.3 automatic polarity recognition to accommodate any standards that empl oy the polarity of the h and v sync signals to indicate the format of the display, the gs4901b/GS4900B will recognize h and v sync polarity and automatically synchronize to the leading edge. the polarities of the hsync and vsync signa ls are reported in bits 3 and 4 of the video_status register. additionally, bit 2 of this register reports the detection of either analog or digital input timing. see section 3.10.3 on page 66 for detailed register descriptions. 10fid input horizontal sync input total line line 1, frame 1 every 'n' frames line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 42 of 95 3.5 reference format detector the reference format detector checks the validity and analyzes the format of the input reference signal. it is designed to accurately differentiate between 59.94 and 60hz frame rates. as described in section 1.4 on page 20 , the gs4901b / GS4900B will automatically recognize the sd video stan dards defined by vid_std[5:0] = 1 to 10. however, in order to enable the device to recognize and lock to any of the hd reference formats defined by vid_std[5:0] = 11 to 38, the user must set the corresponding bit low in the reference_standard_disable register, located at address 11h-13h of the host interface. the user must also set the hd_reference_enable bit of register 82 h[7] high. see the description of the reference_standard_disable and hd_reference_enable registers in section 3.10.3 on page 66 . 3.5.1 horizontal and vertical timing characteristic measurements when a reference signal is applied to the designated input pins, the gs4901b/GS4900B will analyse the signal and report the following in registers 0ah to 0eh of the host interface: ? the number of 27mhz clock pulses between leading edges of the h input reference signal (h_period register) ? the number of 27mhz clock pulses in 16 horizontal periods (h_16_period register) ? the number of h reference pulses between leading edges of the v input reference signal (v_lines register) ? the number of h reference pulses in two vertical periods (v_2_lines register) ? the number of h reference pulses in one f period (f_lines register) these parameters may be read via the host interface and are used by the device to determine reference signal validity.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 43 of 95 3.5.2 input reference validity before the device attempts to operate in genlock mode, the input signals applied to hsync and vsync must be valid (sd re ferences only) and must conform to one of the recognized and enabled video standards, as described in section 1.4 on page 20 . for an sd input reference signal to be considered valid, the periodicity of hsync must be between 29.66u s and 70us, and the periodicity of vsync must be between 16ms and 25ms. the fsync signal is not essential for validity. the ref_lost pin will be set low once the sd input reference sign al is determined to be valid. for hd input reference signals where the user has set the hd_reference_enable bit of register 8 2h[7] high, the device will not measur e signal validity. in this case, the ref_lost pin will be low whenever any reference signal is present on the input. the device then compares the timing parameters of the input reference signal to each of the video standards that has been enabled in the the reference_standard_disable register (there may be up to 36 video standards if all hd standards are enabled). th e device will then determine if the input reference is one of the enabled and recognized standards. if it is, the vid_std[5:0] value for the format is written to the input_standard register at address 0fh of the host interface. if the reference format is unre cognized or disabled, 00h is programmed in this register. once a reference signal is recognized by the device, vsync and fsync will no longer be monitored. loss of signal on these pins will not af fect the operation of the device. if the ref_lost pin is high, or if the input signal is unrecognized as one of the enable video formats, the genlock pin should not be set low. the ref_lost output pin may also be read via bit 0 of the genlock_status register (see section 3.10.3 on page 66 ). 3.5.2.1 ambiguous standard selection there are some standards with identical h, v, and f timing parameters, such that the gs4901b/GS4900B?s reference format detector cannot distinguish between them. table 3-2 groups standards with shared h, v, and f periods. using the amb_std_sel register at address 10h of th e host interface, the user may select their choice of standard to be identified with a particular set of measurements. for example, to have 1716 clocks of 27mhz per line with 525 lines per frame identified as 4fsc 525, program amb_std_sel[10:0] = xxx10 xxxxxx, where ?x? signifies ?don?t care?.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 44 of 95 3.5.3 behaviour on loss and re-acq uisition of the reference signal by default, the gs4901b/g s4900b will ignore one missing h pulse on the hsync pin and will continue to ope rate in genlock mode (a lthough the lock_lost pin will temporarily be set high). this behavi our is controlled by the run_window bits of register address 24h. if there are two consecutive missing h pulses on the hsync input pin, the ref_lost and lock_lost pins will both go high and the device will enter freeze mode. an internal flywheel ensures the selected output clock and timing signals maintain their previous phase and frequency and continue to operate without glitches. the vsync and fsync signals ar e not monitored in genlo ck mode; loss of signal on these pins will not affect the operation of the device. note 1: if the input reference is removed and re-applied, all line-based timing outputs will be inaccurate for up to one frame fo r all output standards. table 3-2: ambiguous standard identification number standard h (27mhz clocks) 16_h (27mhz clocks) v (lines) f (lines) amb_std_sel[10:0] 1 1920x1080/60/2:1 interlace (25) 800 12800 562.5 1125 x x x x x x x x x 0 0 1920x1080/30/psf (30) 800 12800 562.5 1125 x x x x x x x x x 0 1 1920x1035/60/2:1 interlace (19) 800 12800 562.5 1125 x x x x x x x x x 1 0 2 1920x1080/59.94/2:1 interlace (26) 800.8 12813 562.5 1125 x x x x x x x 0 0 x x 1920x1080/29.97/psf (32) 800.8 12813 562.5 1125 x x x x x x x 0 1 x x 1920x1035/59.94/2:1 interlace (20) 800.8 12813 562.5 1125 x x x x x x x 1 0 x x 3 1920x1080/50/2:1 interlace (27) 960 15360 562.4 1125 x x x x x 0 0 x x x x 1920x1080/25/psf (34) 960 15360 562.4 1125 x x x x x 0 1 x x x x 4 601 525 / 2:1 interlace (3) 1716 27456 262.5 525 x x x 0 0 x x x x x x 720x486/59.94/2:1 interlace (7) 1716 27456 262.5 525 x x x 0 1 x x x x x x 4fsc 525 / 2:1 interlace (1) 1716 27456 262.5 525 x x x 1 0 x x x x x x 601 - 18mhz 525/2:1 interlace (5) 1716 27456 262.5 525 x x x 1 1 x x x x x x 5 601 625 / 2:1 interlace (4) 1728 27648 312.5 625 x 0 0 x x x x x x x x 720x576/50/2:1 interlace (8) 1728 27648 312.5 625 x 0 1 x x x x x x x x composite pal 625/2:1/25 (2) 1728 27648 312.5 625 x 1 0 x x x x x x x x 601 - 18mhz 625/2:1 interlace (6) 1728 27648 312.5 625 x 1 1 x x x x x x x x 6 rsvd rsvd rsvd rsvd rsvd 0 x x x x x x x x x x 720x483/59.94/1:1 progressive (9) 858 13728 525 525 1 x x x x x x x x x x ?x? signifies ?don?t care.? the x bit wi ll be ignored when determining which standard to select in each of the 6 groups above. note: when the sd input reference format of 720x483/59.94/1:1 (vid_s td = 9) is applied to the input, the user must set bit [15] of the of the amb_std_sel register address to '1' before the device will recognize this reference.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 45 of 95 note 2: when locking the sd input refe rence standards 3, 5, 7, or 9 to the ?f/1.001? hd input reference standards, there may be a random phase difference between the input vsync and output v sync signals occuring each time the input reference is removed and re-a pplied. this will affect a ll line-based timing outputs. the user may reset the line-based counters after the reference is re-applied without disrupting the pixel or audio clocks by toggling bit 15 of register address 83h in the host interface. this will ca use the input vsync an d line-based timing output signals to take on their default timi ng relationship, as described in note 3 of section 3.2.1.1 on page 35 . re-acquisition of the same reference upon re-application of the reference signal, the device checks whether the reference has drifted more than +/- 2us from its expected location by comparing the current relative position of the h pulses with the previous position, over a 16-line interval. if the reference returns with the h pulses in the expected location +/- 2us, the pll will drift lock and the clock generator will co ntinue to operate without a glitch. the ref_lost and lock _lost pins will be set back low. if the reference returns with the h pulses outside the +/- 2us window, the device will crash lock the output timing to the new input phase. the principles of crash lock and drift lock are described in section 3.6.1 on page 47 . note: to resume proper genlock operation upon re-application of the reference signal, the user must implement the follo wing register manipulation every time the reference is removed and re-applied: 1. read the value contained in register address 24h 2. clear the run_window bits [2:0] of register 24h 3. re-write the value read in step 1 to register address 24h. this procedure will force the device to lo ck to the reference as described above, but will maintain the flywh eeling capability of the gs 4901b/GS4900B should a single missing h pulse occur in the genlocked state. to avoid the above procedure, the user ma y choose to clear the run_window bits [2:0] of register addr ess 24h upon power-up or reset. however, this will disable the flywheeling feature of the device that allows it to maintain genlock through one missing input h pulse. acquisition of a new reference when a new reference is applied, the device continues to operate in freeze mode while the reference format detector checks for validity as described in section 3.5.2 on page 43 . once validity is detected, the ref_lost pin is set low. assuming genlock is low, the device will then attempt to genlock the selected output clock and timing signals to the new input reference. if the output can be automatically genlocked to the new inpu t reference, lock_l ost will go low and the device will re-enter genlock mode. ot herwise, the lock_lo st pin will remain high and the device w ill enter free run mode.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 46 of 95 3.5.4 allowable frequency drift on the reference by default, the frequency of the refere nce h pulse on hsync may drift from its expected value by approximately +/- 0.2% before the internal video pll loses lock. this tolerance may be adjusted using the max_ref_delta register at address 1eh of the host interface. the encoding scheme is shown in table 3-3 . the default value of the register is bh. note: regardless of the setti ng of this register, the de vice will always differentiate between 59.94hz and 60hz reference standards. 3.6 genlock when both the ref_lost output and the genlock input are low, the device will attempt to genlock the output clock an d timing signals to the input reference. note: the user must apply a reference to the input of the device prior to setting genlock = low. if the genlock pin is set low and no reference signal is present, the generated clock and timing ou tputs of the device may correspond to the internal default settings of the chip until a reference is applied. once reference validity is established and the reference format is recognized, the device uses an internal cross-reference genlock look-up table to determine whether the input can be used to genlock the output. a simplified version of this look-up table is shown in table 3-4. the table represents a matrix with the vid_std[5:0] number representation of each possible reference format along the top axis, and the vid_std[5:0] representation of each possible output timing format along the vertical axis. a shaded box indicates that the output format can be automatically genlocked to the input reference. table 3-3: max_ref_delta encoding scheme register setting maximum allowable frequency drift register setting maximum allowable frequency drift 0h +/- 2 -20 8h +/- 2 -12 1h +/- 2 -19 9h +/- 2 -11 2h +/- 2 -18 ah +/- 2 -10 3h +/- 2 -17 bh +/- 2 -9 4h +/- 2 -16 ch +/- 2 -8 5h +/- 2 -15 dh +/- 2 -7 6h +/- 2 -14 eh +/- 2 -6 7h +/- 2 -13 fh +/- 2 -5 the maximum allowable frequency drift is measured as a fraction of the frequency of the reference h pulse.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 47 of 95 if the device determines that the output can be automatically genlocked to the input reference, it will lock the outp ut format to the reference, adjust the output timing signals based on the genlock timing offset r egisters (section 3.2. 1.1 on page 37), and then set the lock_lost pin low. if the device cannot automat ically genlock the output to the applied reference, the lock_lost pin will be set high and the device will operate in free run mode. individual h, v, and f-locked signals can be read from the genlock_status register of the host interface. additi onally, designated bits in the genlock_control register may be configured to permit the genlock block to ignore invalid timing on the hsync, vsync, or fsync pi n when determining th e locked status of the device. these registers are described in section 3.9.3 on page 66. the user may disable one or more of the 36 video standards listed in table 1-2 from being used to genlock the output by setting the reference_standard_disable register located at address 11h-13h of the host interface. if a reference is applied that is disabled in the re ference_standard_dis able register, the lock process will fail when the application layer sets genlockb = low. note: if the device is already genlocked to an input reference and the applied standard is subsequently disabled in the reference_standard_disable register, the device will remain locked. by default, the hd video reference formats are disabled in the reference_standard_disable register and so must be enabled by the user before attempting to lock to an hd reference. see section 1.4 on page 20 . 3.6.1 adjustable locking time the gs4901b/GS4900B offers two different locking mechanisms to allow the user to control the pll lock time and the inte grity of the output signal during the locking process. the locking process is said to ta ke place after the application of the input reference and before the lock_lost signal is set low. by default, the internal pll will crash lock. this locking process will ensure a minimum pll locking time; however, crash lock will cause the pha se of the output clock and timing signals to jump during the locking process. the crash behaviour of the video pll is controlled by the cr ash_time bits of register address 24h. alternatively, the user may set bit 1 of re gister 16h high to force the pll to drift lock. drift lock will increase the locking time of the pll, but will maintain the signal integrity of the output clock and timing pulses during the locking process. table 3-4: cross-reference genlock table input reference format 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 29 30 31 32 33 34 35 36 37 38 1 3 4 5 6 7 8 9 10
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 48 of 95 as discussed in section 3.5.3 on page 44 , the device will normally drift lock when the reference is removed and subsequently re-applied during genlock mode. 3.6.2 adjustable loop bandwidth the default loop bandwidth of the gs4901b/ GS4900B's internal video pll is 10hz when the output video standard is the same as the input reference format. for other cross-locking combinations, the defaul t loop bandwidth ma y be smaller than 1hz or as large as 30hz. the user may adjust the loop bandwidth of both the video and audio plls depending on the input, output, and audi o standards selected. increasing the loop bandwidth will result in a shorter pll lo ck time, but will allow more frequency components of jitter to be passed to the outputs. decreasing the loop bandwidth will decrease the output jitter, but will result in a longer pll lock time. 3.6.2.1 loop bandwidth of the video pll the capacitive component of the filter controlling the video loop bandwidth is determined by the video_cap_genlock re gister and the resistive component is determined by the video_res_genlock re gister. these two registers are located at addresses 26h and 27h, respectively, of the host interface. to determine the setting of video_res_genlock and video_cap_genlock, the following equations must be solved: where: bw = the desired video pll loop bandwidth jitterin = jitter present on applied hsync reference signal, in seconds h_feedback_divide = the numerator of the video pll divide ratio h_feedback_divide represents the numerato r of the ratio of the output clock frequency to the frequency of the h reference signal. video_res_genlock 47 log 2 6 bw jitterin h_feedback_divide () + = video_cap_genlock video_res_genlock 21 ?
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 49 of 95 for example, to program a loop bandwidth of 25hz given a 54mhz video clock and a reference with a 27mhz video clock and 1716 clocks per line, the following steps are necessary: 1. calculate h_feedback_divide: therefore, h_feedback_divide = 1716. 2. calculate the value for video_res_genlock: 3. calculate the value for video_cap_genlock: therefore, program video_res_genlo ck = 37 and video_cap_genlock = 16. note: the value programmed in the vi deo_res_genlock register must be between 32 and 42. the value programmed in the video_cap_genlock register must be greater than 10. these limits define the exact range of loop bandwidth adjustment available. 3.6.2.2 loop bandwidth of the audio pll (gs4901b only) the capacitive component of the filter controlling the audio loop bandwidth is determined by the audio_cap_genlock re gister and the resistive component is determined by the audio_res_genlock re gister. these two registers are located at addresses 39h and 3ah, resp ectively, of the host interface. h_feedback_divide h_reference_divide ------------------------------------------------- - f pclkout f hrefin ----------------- f pclkout 27 mhz = f hrefin 27 1716 ----------- - mhz = h_feedback_divide h_reference_divide ------------------------------------------------- - 27 1716 27 ----------- - 1716 1 ----------- - = = video_res_genlock 47 log 2 625 310 9 ? () 1716 () + 37 == video_cap_genlock 37 21 ? 16 ==
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 50 of 95 to determine the setting of audio_res_genlock and audio_cap_genlock, the following equations must be solved: where: bw = the desired audio pll loop bandwidth jitterin = jitter present on output pclk, in seconds. a_feedback_divide = the numerator of the audio pll divide ratio a_feedback_divide is defined by the following equation: where f s is the fundamental audio sampling frequency and f out is the output video clock frequency. the intege r constant, n, will depend on the fundamental audio sampling frequency as shown in table 3-5 . note: the value programmed in the audio_res_genlock register must be between 32 and 42. the value programmed in the audio_cap_genlock register must be greater than 10. these limits define the exact range of loop bandwidth adjustment available. table 3-5: integer constant value asr_sel[2:0]=100b enable_384fs = 0 value of constant (n) no x 3072 yes yes 1024 yes no 1536 notes: 1. enable_384fs corresponds to bit 5 of address 31h of the host interface. it is low by default. 2. ?x? signifies ?don?t care.? this bit will be ignored when determining n. audio_res_genlock 47 log 2 6 bw jitterin a _feedback_divide () + = audio_cap_genlock audio_res_genlock 21 ? a _feedback_divide a_reference_divide ------------------------------------------------- - n f s f out -------- =
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 51 of 95 3.6.3 locking to digital timing from a deserializer as described in section 3.4.1 on page 40 , the gs4901b/GS4900B may be genlocked to either an analog reference, such as a black & burst signal, or to an sdi input via the digital h, v, and f blanking signals normally produced by a deserializer. when locking to an sdi input, the user sh ould consider the possibility of a switch of the sdi signal upstream from the system. if the gs4901b/GS4900B is locked to the digital h, v, and f blanking signals produced by a deserializer, and the sdi input to the deserializer is switched such that the phase of the h in put changes abruptly, the re f_lost output will remain low and the gs4901b/GS4900B will not cras h lock to the new h phase. in stead, the clock and timing outputs will very slow ly drift towards the new phase. during this period of drift, the lock_lost outp ut will be low, even though the device is not genlocked. the user should clear the run_window bits [2:0] of register adress 24h to force the device to crash lock sh ould such a switch o ccur. this will cause the gs4901b/GS4900B to crash lock whenever it sees a disturbance of the input h signal. note: any action that causes an abrupt phase change of the h input to the gs4901b/GS4900B such that ref_lost is not triggered will cause the device to respond in the manner described above. in addition to the slow drifting beha viour outlined above, there may also be a random phase difference between the input vsync an d output v sync signals occurring each time a switch in the sdi stream causes an ab rupt phase change of the h input to the gs4901b/g s4900b. this will only occur when attempting to lock the 525-line sd output standards to the " f/1.001 " hd input reference standards. all line-based timing outputs are affected. the only way to ensure a constant phase difference between the input vsync signal and the line-based timing outputs is to reset the line-based counters after such a switch occurs. this is acheived by toggling bit 15 of register address 83h in the host interface. the devi ce will then delay all line-based output timing signals by vsync lines relative to the input vsync reference, as described in note 3 of section 3.2.1.1 on page 35 .
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 52 of 95 3.7 clock synthesis the clock synthesis circuit generates the video clocks based on the vid_std[5:0] pins and host register settings. in the gs4901b, the clock synthesis circuit also generates the audio clock signals base d on the asr_sel[2:0] pins and host register settings. the generated video and audio clocks may be further divided and are presented to the application layer via pins pclk1- pclk3 and aclk1-aclk3 respectively. 3.7.1 video clock synthesis the video clock generat or is referenced to an internal crysta l oscillator and is responsible for generating the pclk output signals. the crystal oscillator requires an external 27mhz crystal connected to pins x1 and x2, or can be driven at lvttl levels from an external 27mhz source connected to x1. these two configurations are shown in figure 1-1 . four different video sample clock rates may be selected using the vid_std[5:0] pins of the device. section 1.4 on page 20 lists the video formats available using the vid_std[5:0] pins. if desired, the external vid_std[5:0] pins may be ignored by setting bit 1 of the video_control register, and the video standard may instead be selected via the vid_std[5:0] register of the host interface (see section 3.10.3 on page 66 ). although the external vid_ std[5:0] pins will be ignore d, they should not be left floating. once the video clock has be en generated, it will be pres ented to the application layer via the pclk1 to pclk3 pins. by def ault, each of the 3 video clock outputs will produce the generated fundamental clock frequency. however, it is possible to select other rates for each pclk output by programming the pclk_phase/divide registers beginning at address 2ch of the host interface (see section 3.10.3 on page 66 ). each pclk output may be individually programmed to provide one of the following: ? pclk fundamental frequency ? fundamental frequency /2 ? fundamental frequency /4 when all six vid_std[5:0] pins are set low, the video clocks will be disabled. pclk1 and pclk2 will go low and pclk3/pclk3 will be high impedance. note: if the pclk divider bits of register s 2ch - 2eh are set to enable a divide by 2 or divide by 4, the resultant divide d clock will align with t he falling edge of the output h sync timing signal eit her on its rising or falling edge.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 53 of 95 the pclk1 to pclk3 outputs may also be individually delayed with respect to the eight timing_out signals to allow fo r skew control downstream from the gs4901b/GS4900B. using the pclk_phase/ divide registers, the phase of each clock may be delayed up to a nominal 10.3ns in 16 steps of approximately 700ps each ( table 3-6 ). this delay is available in addi tion to the genlock timing offset phase adjustment described in section 3.2.1 on page 35 . additionally, the current dr ive capability of pclk1 and pclk2 may be set high or low using the pclk_phase/divide register s. by default the current drive will be low. 3.7.2 audio clock synt hesis (gs4901b only) the audio clock generator is referenced to the internal pclk signal and is responsible for generating the aclk output signals. three audio clock output pins, aclk1 to aclk3, are available to the application layer. the fundamental sampling frequency, fs, is selected using th e asr_sel[2:0] pins as shown in table 3-7 . if desired, the external asr_sel[2:0] pins may be ignored by setting bit 2 of the audio_control register and the sampling frequency may instead be programmed in the asr_sel[2:0] register of the host interface (see section 3.10.3 on page 66 ). although the external asr_ sel[2:0] pins will be ignored, they shou ld not be left floating. table 3-6: video clock phase adjustment host settings pclkn_phase[3:0] setting 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh phase increment (ns) 0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0 7.7 8.4 9.1 9.8 10.3 notes: 1. the phase increments listed above are nominal values. 2. the phase of pclk is delayed relative to the timing_out pins.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 54 of 95 when all three asr_sel[2:0] pins are se t low, the audio clock outputs will be high impedance. in this case, the application layer may continue to power the aud_pll_vdd pin; however, to mini mize noise and power consumption, aud_pll_vdd may be grounded. by default, after system reset, aclk1 to aclk3 will output clock signals at 256fs, 64fs, and fs respectively. different divi sion ratios for each output pin may be selected by programming the aclk_fs_mu ltiple registers beginning at address 3fh of the host interface (see section 3.10.3 on page 66 ). the encoding of this register is shown in table 3-8 . clock outputs of 512fs, 348fs, 256fs, 192fs, 128fs, 64fs, fs, and z bit are select able on a pin by pin basis. the z bit will go high for one fs period every 192 fs periods. its phase is not defined by any timing event in the gs4901b, and so is arbitrary. table 3-7: audio sample rate select asr_sel[2:0] sampling frequency (khz) 000 audio clock generation disabled 001 32 010 44.1 011 48 100 96 101 slow 32* 110 slow 44.1* 111 slow 48* *slow 32, 44.1, and 48 are available only when the video standard selected is 23.98, 29.97, or 59.94 frame rate based. they refer to 32khz, 44.1khz, or 48khz multiplied by 1000/1001 to maintain the 1, 2, or 3 frame sequence normally associated with 24, 30, and 60 fps video. table 3-8: audio clock divider aclkn_fs_multiple[3:0] audio clock frequency 000 fs 001 64fs 010 128fs 011 192fs* 100 256fs 101 384fs* 110 512fs** 111 z-bit *this setting is only available when the enable_384fs bit of the audio_control register is high. **512fs clock will have a 33% duty cycle wh en the enable_384fs bit is high and fs = 96khz.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 55 of 95 the fs signal on aclk1-3 ha s an accurate 50% duty cycle, and can be used for left/right definition, with the following ex ception: if fs = 96khz and the user configures the host interface such that one of the three aclk pins is set to output a clock signal at 192fs or 384fs, the 512fs clock will have a 33% duty cycle. all audio clocks are initially reset on the risi ng edge of the afs pu lse, ensuring that video to audio clock synchronization is co rrect. during normal operation, the audio clock edge is allowed to drif t slightly with respect to th e afs pulse. by default, the audio clock will be reset directly by th e afs pulse if it drifts more than approximately +/-0.1us from the rising edge of the afs pulse. however, after device reset, or after the application of a new input reference, the aclk outputs may sometimes be offset from the afs pulse by up to several microseconds. the offset will remain until the device is rese t or the reference re moved and re -applied. the user may avoid this offset by mini mizing the width of the afs_reset_window using bits 9-7 of register 31h for the duration of the audio pll locking process. once the audio pll is locked, bit 1 of register 1fh will be set high, and the afs_reset_window may be set as desired. see table 3-9 . 3.7.2.1 audio to video clock phasing the important aspect of the audio to video phase relates to the way in which the afs pulse is used to reset the audio clock dividers so as to line up the leading edge of the audio clocks with the leading edge of the h sync pulse on line 1 of the first field in the audio frame sequence. the afs pulse is further discussed in section 3.8.2 on page 58 . 625i 50 format for the 48khz sampling rate, the audio to video phase relationship for 625/50i reference signals is provided by the device in accordance with the ebu recommended practice r83-1996. the start of an audio frame (fs clock) will align with the 50% point of the h sync input of line 1 of each video frame (+/- the allowable drift specified in table 3-9 ). table 3-9: encoding scheme for afs_reset_window window tolerance (us) afs_reset_window (address 31h) fs = 32khz fs = 44.1khz fs = 48 khz fs = 96 khz (enable_384fs = 1) fs = 96 khz (enable_384fs = 0) 000 0.044 0.033 0.030 0.030 0.044 001 0.084 0.062 0.057 0.057 0.084 010 (default) 0.166 0.121 0.112 0.112 0.166 011 0.329 0.239 0.220 0.220 0.329 1xx 0.654 0.475 0.437 0.437 0.654 note: ?x? signifies ?don?t care.? the bit setting will be ignored.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 56 of 95 525i 59.94 format for 525/59.94 ntsc refe rence signals, t he device will observe the 5-frame phase-relationship inherent with this video standard, aligning the audio clocks with the 50% point of the h sync input of line 1 on every fifth frame (+/- the allowable drift specified in table 3-9 ). the number of audio sample clocks during a video frame is shown in table 3-10 for 32, 44.1, and 48khz audio sampling frequencies. the external 10fid input pin may be us ed to resynchronize other audio clock frequencies, according to table 3-10 , by applying an active signal during the reference hsync of line 1 of the ap propriate video frame. please see section 3.4.2 on page 41 for more details on the 10fid input pin. in the case where 10fid is not present as a refere nce signal, the gs4901b will automatically generate an afs pulse appropriate to the format selected, and use it to create an audio frame sequence. host interface control of afs and 10fid alternatively, the user may program the devi ce via the host interface to re-time the audio frame sequence and 10 field-id. using register 1ah, a pulse may be generated to reset the afs and/or 10fid divi ders at the start of an output video frame (see section 3.10.3 on page 66 ). if using the host interface to reset the afs pulse, the device may be configured to ignore the input 10fid reference pin. to di sable the signal on the external 10fid pin from resetting the afs output pulse, set bit 0 of the audio_control register high. if using the host interface to reset the 10f id pulse, the external 10fid pin must be grounded. table 3-10: audio sampling frequency to video frame rate synchronization audio samples per video frame audio sample rate (khz) 24fps 25fps 29.97fps 30fps 50fps 59.94fps 60fps 32 4000/3 1280 16016/15 3200/3 640 8008/15 1600/3 44.1 3675/2 1764 147147/100 1470 882 147147/200 735 48 2000 1920 8008/5 1600 960 4004/5 800 * fps = frames per second.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 57 of 95 3.8 video timing generator the internal pclk signal generated by th e clock synthesis circuit is used to produce horizontal, vertical, and frame based timing output signals. the signals generated and available to th e application layer via the timing_out pins are: h sync, h blanking, v sync, v blanking, f sync, f digital, de, 10fid, afs (gs4901b only), and user_1~4. these signals are defined in section 1.5 on page 24 . additional information pertaining to the 10fid, afs, and user_1~4 signals can be found in the sub-sections below. when the gs4901b/GS4900B is operatin g in genlock mode, the h, v, and f based output timing signals are synchroniz ed to the h, v, and f reference signals applied to the inputs by the applicatio n layer. the video timing outputs may be offset from the input reference by pr ogramming the genlock offset registers beginning at address 1bh of the host interface (see section 3.2.1.1 on page 35 ). all timing_out signals have selectable pol arity. the default polarities for each signal are given in the descriptions in section 1.5 on page 24 . 3.8.1 10 field id pulse as described in table 1-3 , the 10 field id (10fid) outp ut signal is used in the identification of film to video cadence. it is only generated for 29.97, 30, 59.94, and 60fps formats. the 10fid pulse is generated on every 5 th frame for 29.97 and 30fps formats, and every 10 th frame on 59.94 and 60fps formats. by default, the 10fid signal is set high on the leading edge of the h sync output for the duration of line 1 of field 1 at the st art of the 10 field se quence. this is shown in figure 3-6 . alternatively, by setting bit 4 of the video _control register at address 4ch of the host interface, the 10fid output signal may be configured to go high (default polarity) on the leading edge of the h sync pu lse of line 1 of the first field in the 10 field sequence, and be reset low on the leading edge of the h sync pulse of line 1 of the second field in the 10 field sequence. this is shown in figure 3-7 . figure 3-6: default 10fid output timing 10fid output horizontal sync output total line line 1, frame 1 every 'n' frames line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 58 of 95 figure 3-7: optional 10fid output timing the phasing of the divide by n frame counte r may be reset by an external pulse on the 10fid input pin, or via register 1ah of the host interface (see section 3.10.3 on page 66 ). note: if a 10fid input signal is not provid ed to the device, the 10fid output signal will be invalid until the user init iates a reset via the host in terface. the user should also reset the 10fid signal via the host if at any time the h input reference signal is removed and then re-applied. 3.8.2 audio frame synchronizin g pulse (gs4901b only) as described in table 1-3 , the audio frame synchronizing (afs) pulse identifies the frame, within an n frame sequence, in whic h the audio sample rate clock is aligned with the h sync of line 1. it is generated for all video formats. the leading edge of the afs output pulse is co-timed with the h sync corresponding to line 1 of every n th frame in the sequence, and therefore identifies the exact time at which the audio sample rate clock and video pclk have synchronous leading edges. the number of frames in the sequence, n, is determined by the video frame rate and the audio clock frequency. these are selected using the vid_std[5:0] and asr_sel[2:0] pins or via the host interface. by default, the afs pulse is 1 line long, as shown in figure 3-8 . alternatively, by setting bit 1 of the audio_control register , the afs output signal may be configured to go high on the leading edge of the h sy nc pulse of line 1 of the first field in the ?n? frame sequence, and be reset low on the leading edge of the h sync pulse of line 1 of the second field in the sequence. the afs timing in this configuration is similar to the 10fid optional timing shown in figure 3-7 . 10fid output horizontal sync output total field line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 59 of 95 figure 3-8: afs output timing the phasing of the divide by n counter ca n be controlled by the 10fid input or via designated registers in the host interface. by default, the 10fid input pin controls the afs phase (in addition to controlling the 10fid phase); however, this feature may be disabled by setting bit 0 of the audio_control register (see section 3.10.3 on page 66 ). in addition, the afs signal may be reset via register 1ah. 3.8.3 user_1~4 as described in table 1-3 , the gs4901b/GS4900B offers 4 user programmable output signals which are ava ilable independent of the se lected output video format. each user signal is individually progra mmable and the polarity, position, and width of each output may be defined with respect to the digital output timing of the device. each output signal may be programmed in both the horizontal and vertical dimensions relative to the leading edges of h blanking and v blanking. if desired, the pulses produced may then be combined with a logical and, or, or xor function to produce a composite signal (f or example, a horizontal back porch pulse during active lines only, or the active part of lines 15 through 20 for vertical information retrieval). by default, the and, or, and xor func tions are disabled. therefore, when a user signal is selected using the output_sel ect registers of the host interface, the signal will go low (default polarity) at the h_start pixel and return high after the h_stop pixel. setting the and bit high, for example, will cause the user signal to be active only when user_h is active and user_v is active (i.e. the pixel is between both h_start and h_stop and v_start and v_stop). see figure 3-9 . note: the effective horizontal range of th e four user-defined timing signals is [h_start + 1, h_stop], except when h_st art = 1, in which case the range is [h_start, h_stop]. this prevents the user from specifying an output user signal that begins on pixel 2 of a line. afs_out horizontal sync output total line line 1 every n frames where: n = 1 @ 25fps: fs = 32khz n = 1 @ 25fps, 30fps & 60fps: fs = 44.1khz n = 1 @ 25fps, 30fps & 60fps; fs = 48khz n = 2 @ 24fps; fs = 44.1khz, 48khz n = 3 @ 24fps, 30fps & 60fps: fs = 32khz n = 5 @ 29.97fps & 59.94fps; fs = 48khz n = 15 @ 29.97fps & 59.94fps; fs = 32khz n = 100 @ 29.97fps; fs = 44.1khz n = 200 @ 59.94fps; fs = 44.1khz
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 60 of 95 in the case of interlaced output format s, the programmed vertical start and stop lines refer to the start and stop lines of the generated user signal on the odd fields. the start and stop lines of the user signal on the even fields will be v_start - 1 and v_stop - 1, respectively. for example, if vid_std[5:0] = 3, the odd fields will ha ve 263 lines and the even fields will have 262 lines. a user-defined ve rtical pulse programmed to start on line 12 and stop on line 17 will st art on frame lines 12 and 2 74, and stop on frame lines 17 and 279. the designated registers for programming ea ch user signal are located in the host interface beginning at address 57h. see section 3.10.3 on page 66 . figure 3-9: user programmable output signal and=0, or=0, xor=0 (default) and=0, or=1 shading indicates when user_x signal is active h_start h_stop v_start v_stop and=1 h_start h_stop v_start v_stop h_start h_stop v_start v_stop and=0, or=0, xor=1 h_start h_stop v_start v_stop
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 61 of 95 3.8.4 timing_out pins the horizontal, vertical, and frame based timing output signals for the selected video format are available to the application layer via the timing_out_1 to timing_out_8 pins. programmable crosspoint switch each timing_out pin outputs a default signal as shown in table 1-3 . alternatively, a crosspoint switch may be programmed via the eight output_select registers of the host interface, allowing th e user to select which output signal is directed to each timing_out pin (see section 3.10.3 on page 66 ). any signal may be sent to more than one pin if desired. table 3-11 outlines the encoding scheme of th e eight output_sel ect registers, which begin at address 43h of the host interface. 3.8.4.1 selectable current drive and polarity the current-drive of each timing output pin is also selectable via the output_select registers. the current drive of each timi ng_out pin is low by default. however, it may be set high to accommodate certain applications. additionally, the polarity register of the host interface may be programmed to select the polarity of each timing output signal. table 3-11: crosspoint select output_select_n bit settings output signal 0000 high impedance 0001 h sync 0010 h blanking 0011 v sync 0100 v blanking 0101 f sync 0110 f digital 0111 10fid 1000 de 1001 reserved 1010 afs* 1011 user_1 1100 user_2 1101 user_3 1110 user_4 1111 reserved *afs is only available on the gs4901b. the bit setting 1010b will be ignored by the GS4900B.
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 62 of 95 3.9 extended audio mode for hd de mux using the gennum audio core the gs4901b/GS4900B has been designed to interface with gennum's fpga audio core in order to provide a 24.576mhz clock (512 * 48khz) locked to the audio clock contained in the embedded audi o data packets of an hd-sdi stream. it is the responsibility of th e user to divide this clock by 4 to obtain the 6.144mhz required by the core. in hd demux mode, the fpga audio core will extract an audio clock from the embedded audio data packets and present a 24khz clock to the gs4901b/GS4900B via the aclkdiv2a (for group a) and aclkdiv2b (for group b) outputs. the embedded clock must be 48khz. the 24khz reference signals for each audi o group must be applied to the hsync input pin of a gs4901b/GS4900B, while a divided version of this signal must be applied to the vsync input pi n. the divided signal must meet the requirements for vsync validity given in section 3.5.2 on page 43 . it is recommended that the vsync signal be generated by dividing the 24khz refere nce applied to hsync by 512 to give 46.875hz. to enable the extended audio mode, the user must do the following: 1. set vid_std[5:0] = 4d. 2. set the f_lock_mask and v_lock_mask bi ts [4:3] of register address 16h to 1. 3. set the ext_audio_mode register address 81h to 20c1h. 4. toggle bit [6] of register address 16h. in this mode, the gs4901b/GS4900B will produce a 24.576mhz clock on its pclk output pins that is locked to the 24khz extracted audio clock reference applied to hsync. it will not lock to any other refe rence frequency. the user may then divide this frequency by 4 using the programmable dividers in the gs4901b/GS4900B. figure 3-10: audio clock block di agram for hd demux operation fpga aout1_ 2 aout3_ 4 aout5_ 6 aout7_ 8 serial video input hd audio demux core pclk gs49xxb video data wclka gs1559 deserializer aclk64a wclkb pclk1 aclk128b aclk64b vin[19:0] pclk aclkdiv2b pclk1 gs49xxb aclk128a aclkdiv2a /512 /512
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 63 of 95 3.10 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the host to enable additional feat ures of the gs4901b/GS4900B and/or to provide additional status information throu gh configuration registers in the device. the gspi comprises a serial data input si gnal, sdin, a serial data output signal, sdout, an active low chip select, cs , and a burst clock, sclk. the burst clock must have a duty cycle between 40% and 60%. because these pins are shared with the jtag interface port, an additional control signal pin, jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pi n is a non-clocked loop-through of sdin and may be connected to the sdin pin of another device, allowin g multiple devices to be connected to the gspi chai n. the interface is illustrated in figure 3-11 . figure 3-11: gspi application interface connection all read or write access to the gs4901b/GS4900B is initiated and terminated by the host processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of interest. th is is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 gs4911b/gs4910b cs gs4911b/gs4910b
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 64 of 95 3.10.1 command word description the command word consists of 16 bits transmitted msb first and includes a read/write bit, an auto-increment bit and a 12-bit address. figure 3-12 shows the command word format and bit configurations. command words are clocked into the gs4901b/GS4900B on the rising edge of the serial clock, sclk, which operates in a burst fashion. when the auto-increment bit is set lo w, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be wri tten into the address specified in the command word, and subseq uent data words will be wri tten into incremental addresses. this facilitates multiple address writes without sending a command word for each data word. auto-increment may be used for both read and write access. figure 3-12: command word format figure 3-13: data word format 3.10.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 3-14 and figure 3-15 respectively. the timing parameters are defined in table 3-12 . when several devices are connected to the gspi chain, only one cs should be asserted during a read sequence. during the write sequence, all command and following data words input at the sdin pin are output at th e sdout pin as is. where several devices are connected to the gspi chain, data can be written simultaneously to all the devices that have cs set low. msb lsb a4 a5 a6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoinc rsv rsv r/w rsv = reserved. must be set to zero. r/w: read command when r/w = 1 write command when r/w = 0 msb lsb d4 d5 d6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 65 of 95 figure 3-14: gspi read mode timing figure 3-15: gspi write mode timing table 3-12: gspi timing parameters parameter definition specification t 0 the minimum duration of time chip select, cs , must be low before the first sclk rising edge. 1.5 ns t 1 the minimum sclk period. 100 ns t 2 duty cycle tolerated by sclk. 40% to 60% t 3 minimum input setup time. 1.5 ns t 4 the minimum duration of time between the last sclk command word (or data word if the auto-increment bit is high) and the first sclk of the data word (write cycle). 37.1 ns t 5 the minimum duration of time between the last sclk command word (or data word if the auto-increment bit is high) and the first sclk of the data word (read cycle). 148.4 ns t 6 minimum output hold time (15pf load). 1.5 ns t 7 the minimum duration of time between the last sclk of the gspi transaction and when cs can be set high. 37.1 ns t 8 minimum input hold time. 1.5 ns sclk cs sdin sdout t 5 t 6 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 3 sclk cs sdin sdout t 0 t 1 t 2 t 4 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 7 t 8
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 66 of 95 3.10.3 configuration and status registers table 3-13 summarizes the gs4901b/GS4900B's internal status and configuration registers. all registers are available to the host via the gspi and are all individually addressable. table 3-13: configuration and status registers register name address bit description r/w default rsvd 00h - 09h ? reserved. ? ? h_period 0ah 15-0 contains the number of 27mhz pulses in the input h sync period. this register is set by the reference format detector block using the h sync signal present on the external hsync input pin. note: if the reference is removed this register will remain unchanged until a new reference with a different hsync period is applied. reference: section 3.5.1 on page 42 rn/a h_16_period 0bh 15-0 contains the number of 27mhz pulses in 16 h sync periods. this register is set by the reference format detector block using the h sync signal present on the external hsync input pin. it is useful for 1/1.001 data detection. note: if the reference is removed this register will remain unchanged until a new reference with a different hsync period is applied. reference: section 3.5.1 on page 42 rn/a v_lines 0ch 15-0 contains the number of h sync periods in the input v sync interval. this register is set by the reference format detector block using the signals present on the external hsync and vsync input pins. note: if the reference is removed this register will remain unchanged until a new reference with a different vsync period is applied. reference: section 3.5.1 on page 42 rn/a v_2_lines 0dh 15-0 contains the number of h sync periods in 2 v sync intervals. this register is set by the reference format detector block using the si gnals present on the external hsync and vsync input pins. note: if the reference is removed this register will remain unchanged until a new reference with a different vsync period is applied. reference: section 3.5.1 on page 42 rn/a f_lines 0eh 15-0 contains the number of h sync periods in the input f sync interval. this register is set by the reference format detector block using the signals present on the external hsync and fsync input pins. note: if the reference is removed this register will remain unchanged until a new reference is applied. if the new reference does not include an fsync pulse, this register will be set to zero. reference: section 3.5.1 on page 42 rn/a
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 67 of 95 input_standard 0fh 15-13 reserved. set these bits to zero when writing to 0fh. ? ? 0fh 12 force_input - set this bit high to force the gs4901b/GS4900B to recognize the applied input reference format as the standard programmed in bits 11-6 of this register. r/w 0 0fh 11-6 forced_standard - when bit 12 is set high, the gs4901b/GS4900B will use the value programmed in these bits, rather than the value in bits 5-0, to determine the input reference format. the 6-bit value programmed here should always correspond to the vid_std[5:0] value of the applied reference. these bits should not be programmed for normal operation. r/w 0 0fh 5-0 detected_standard - contains the video standard applied to the input reference pins once it has been detected. these bits are set by the reference format detector block and correspond to the vid_std[5:0] value of the standard as listed in table 1-2 . the detected_standard bits will be set to zero if no input reference signal is applied or if the input reference signal is not an automatically recognized video format. otherwise the value will be between 1 and 54. reference: section 3.5.2 on page 43 r/w n/a amb_std_sel 10h 15-11 reserved. set these bits to zero when writing to 10h. ? ? 10h 10-0 the user may set this register to distinguish between different formats that look identical to the internal reference format detector block. see table 3-2 . reference: section 3.5.2.1 on page 43 r/w 0 reference_standard_disable 13h-11h 38-0 the reference_standard_disable register may be used to disable/enable one or more of the input standards given in table 1-2 from being recogni zed by the device and used to genlock the output. this is done by setting the bit high that corresponds to the vid_std[5:0] value of the video format. for example, if bit 5 is set high, then the output clock and timing signals will not genlock to an input reference with timing corresponding to vid_std[5:0] = 5 in table 1-2 . likewise, to enable recognition of vid_std[5:0] = 26 (1080i/59.94) as an input reference format, the user must set bit 26 low. address 13h = bits 38-32* address 12h = bits 31-16 address 11h = bits 15-0 *bits 47-39 of address 13h should always be written high. reference: section 3.5 on page 42 r/w ffffh ffffh f800h rsvd 14h ? reserved ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 68 of 95 genlock_status 15h 15-6 reserved. ? ? 15h 5 reference_lock - this bit will be high when the output is successfully genlo cked to the input (i.e. when bits 4-1 of this register are high and are not masked by bits 4-2 of register 16h). the lock_lost output pin is an inverted copy of this bit. reference: section 3.6.1 on page 47 rn/a 15h 4 f_lock - this bit will be high when the output f is successfully genlocked to the fsync input. note: if the input reference does not include an fsync input, this bit will have the same setting as v_lock (bit 3). reference: section 3.6.1 on page 47 rn/a 15h 3 v_lock - this bit will be high when the output v is successfully genlocked to the vsync input. reference: section 3.6.1 on page 47 rn/a 15h 2 h_lock - this bit will be high when the output h is successfully genlocked to the hsync input. reference: section 3.6.1 on page 47 rn/a 15h 1 clock_lock - this bit will be high when the video clock is locked to the internal v_pll and the audio clock is locked to the internal a_pll (i.e. bits 0 and 1 of register 1fh are high). reference: section 3.6.1 on page 47 rn/a 15h 0 reference_present - this bi t will be high when a valid input reference signal has been applied to the device. the ref_lost output pin is an inverted copy of this bit. reference: section 3.5.2 on page 43 rn/a table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 69 of 95 genlock_control 16h 15-7 reserved. set these bits to zero when writing to 16h. ? ? 16h 6 this bit is used to enable the extended audio mode of the device. r/w 0 16h 5 genlock_from_host - set this bit high to enable video genlock control via the host interface instead of the external genlock pin (see bit 0 of this register). reference: section 3.2 on page 34 r/w 0 16h 4 f_lock_mask - if this bit is set high, the gs4901b/GS4900B will ignore the status of f_lock (bit 4 of register 15h) when determining the status of reference_lock (bit 5 of register 15h). reference: section 3.6.1 on page 47 r/w 0 16h 3 v_lock_mask - if this bit is set high, the gs4901b/GS4900B will ignore the status of v_lock (bit 3 of register 15h) when determining the status of reference_lock (bit 5 of register 15h). reference: section 3.6.1 on page 47 r/w 0 16h 2 h_lock_mask - if this bit is set high, the gs4901b/GS4900B will ignore the status of h_lock (bit 2 of register 15h) when determining the status of reference_lock (bit 5 of register 15h). reference: section 3.6.1 on page 47 r/w 0 16h 1 drift_crash - when this bit is set high, the generated video clock will drift lock to a new input reference rather than crash lock. reference: section 3.6.1 on page 47 r/w 0 16h 0 genlock - this bit may be used instead of the external pin to genlock the output video format to the input reference. this bit will be ignor ed if bit 5 of this register is low. reference: section 3.2 on page 34 r/w 0 rsvd 17h-19h ? reserved ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 70 of 95 10fid_afs_reset 1ah 15-4 reserved. set these bits to zero when writing to 1ah. ? ? 1ah 3 afs_reset (gs4901b only) - set this bit high to use reset_sync (bit 0 of register 1ah) to reset the output afs pulse. note: this bit will remain low in the GS4900B. set this bit low when writing to address 1ah of the GS4900B. reference: section 3.7.2.1 on page 55 r/w 0 1ah 2 10fid_reset - set this bit high to use reset_sync (bit 0 of register 1ah) to reset the output 10fid pulse. note: if a 10fid input signal is not provided to the device, the user must generate a reset using this bit to initiate the 10fid timing output. in this case, the 10fid input pin must be grounded. reference: section 3.7.2.1 on page 55 r/w 0 1ah 1 reserved. set this bit to zero when writing to 1ah. ? ? 1ah 0 reset_sync - resets the pu lses described in bits 2, and 3 above. the reset pulse is generated if this bit is pulsed (low to high to low) during the output frame immediately prior to the frame the reset is to occur. this reset will operate independently of any other resets, for example from the reference input. r/w 0 h_offset 1bh 15-0 the output h signal ma y be delayed with respect to the input reference by the numbe r of pixels programmed in this register. (see section 3.2.1.1 on page 35 ). the value programmed in this register should not exceed the maximum number of clock periods per line of the outgoing standard. horizontal advances may be achieved by programming a value equal to the maximum allowable offset minus the desired advance. note: this register is in ternally read by the device once per field. at that time any new value programmed is sent to the internal offset circuitry. reference: section 3.2.1.1 on page 35 r/w 0 v_offset 1ch 15-0 the output v signal ma y be delayed with respect to the input reference by the number of lines programmed in this register. (see section 3.2.1.1 on page 35 ). the value programmed in this register should not exceed the maximum number of lines per frame of the outgoing standard. vertical advances may be achieved by programming a value equal to the maximum allowable offset mi nus the desired advance. note: this register is in ternally read by the device once per field. at that time any new value programmed is sent to the internal offset circuitry. reference: section 3.2.1.1 on page 35 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 71 of 95 clock_phase_offset 1dh 15-0 phase_offset - the output clock and data phase may be offset with respect to the input reference by the number of increments programmed in this register. the increment step size depends on the video clock frequency. the encoding scheme for this register is shown in table 3-1 . note: this register must be cleared to achieve a clock phase offset of zero. reference: section 3.2.1.1 on page 35 r/w 0 max_ref_delta 1eh 15-0 the value programmed in this register controls the allowed deviance from the expected frequency on the reference hsync before the internal video pll loses lock. the encoding scheme is shown in table 3-3 . reference: section 3.5.4 on page 46 r/w 000bh video_status 1fh 15-5 reserved. ? ? 1fh 4 ref_h_polarity - status register to indicate the detected h sync polarity ('1' for positive, '0' for negative). this bit will be zero when no reference signal is present. reference: section 3.4.3 on page 41 rn/a 1fh 3 ref_v_polarity - status register to indicate the detected v sync polarity ('1' for positive, '0' for negative). this bit will be zero when no reference signal is present and for digital blanking input references. reference: section 3.4.3 on page 41 rn/a 1fh 2 ref_blank_timing - status register to indicate the input detection of h blanking vs . h sync timing (?1? for blanking, '0' for sync timing). this bit will be zero when no reference signal is present. reference: section 3.4.3 on page 41 rn/a 1fh 1 a_pll_lock (gs 4901b only)- this bit will be high when the generated audio clock is locked to the video clock reference. note: this bit will remain high in the GS4900B. reference: bit 1 of register 15h. rn/a 1fh 0 v_pll_lock - this bit will be high when the generated video clock is locked to t he h sync input reference. reference: bit 1 of register 15h. rn/a rsvd 20h-23h ? reserved ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 72 of 95 constcf_genlock 24h 15-8 crash_time - cont rols the crash lock period of video pll locking process. this time contributes to the total pll lock time given in the ac characteristics table. the time of the crash process in h reference periods is determined by [crash_time x 4] + 1. the default value of these bits will vary depending on the output video standard selected. reference: section 3.6.1 on page 47 r/w ? 24h 7-3 lock_lost_threshold - contro ls the threshold of the lock indication circuit. a larger value programmed in this register can increase the st ability of the lock_lost output signal when the input h reference signal is subject to large amounts of low frequency jitter. a larger value in this register will al so increase the lock indication time, although not the actual lock time of the device. the default value of these bits will vary depending on the output video standard selected. r/w ? 24h 2-0 run_window - controls the output frequency error in the case of a missing or mis-ti med h reference transition. the default value of this register allows the device to maintain genlock through one missing input h pulse. this feature can be disabled by programming run_window = 000b. in this case, the device will immediately react to any disturbance of the input h signal. the default value of these bits will vary depending on the output video standard selected. reference: section 3.5.3 on page 44 r/w ? rsvd 25h ? reserved. ? ? video_cap_genlock 26h 15-6 reserved. set these bits to zero when writing to 26h. ? ? 26h 5-0 control signal to adjust loop bandwidth of video genlock block. the value programmed in this register must be between 10 and video_res_genlock - 21. the default value of this register will vary depending on the output video standard selected. reference: section 3.6.2 on page 48 r/w ? video_res_genlock 27h 15-6 reserved. set these bits to zero when writing to 27h. ? ? 27h 5-0 control signal to adjust loop bandwidth of video genlock block. the value programmed in this register must be between 32 and 42. the default value of this register will vary depending on the output video standard selected. reference: section 3.6.2 on page 48 r/w ? rsvd 28h-2bh ? reserved ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 73 of 95 pclk1_phase/divide 2ch 15-7 reserved. set thes e bits to zero when writing to 2ch. ? ? 2ch 6 current_p1 - selects the current drive capability of the pclk1 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.7.1 on page 52 r/w 0 2ch 5-2 pclk1_phase - adjusts the output phase of the pclk1 clock with respect to the ti ming output pins. phase is delayed in 700ps (nominal) increments as shown in table 3-6 . reference: section 3.7.1 on page 52 r/w 0 2ch 1 divide_by_4 - set this bit high to divide the output pclk1 by four. note: setting this bit and bit 0 simultaneously high will hold the pclk1 pin low. reference: section 3.7.1 on page 52 r/w 0 2ch 0 divide_by_2 - set this bit high to divide the output pclk1 by two. note: setting this bit and bit 1 simultaneously high will hold the pclk1 pin low. reference: section 3.7.1 on page 52 r/w 0 pclk2_phase/divide 2dh 15-7 reserved. set thes e bits to zero when writing to 2dh. ? ? 2dh 6 current_p2 - selects the current drive capability of the pclk2 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.7.1 on page 52 r/w 0 2dh 5-2 pclk2_phase - adjusts the output phase of the pclk2 clock with respect to the ti ming output pins. phase is delayed in 700ps (nominal) increments as shown in table 3-6 . reference: section 3.7.1 on page 52 r/w 0 2dh 1 divide_by_4 - set this bit high to divide the output pclk2 by four. note: setting this bit and bit 0 simultaneously high will hold the pclk2 pin low. reference: section 3.7.1 on page 52 r/w 0 2dh 0 divide_by_2 - set this bit high to divide the output pclk2 by two. note: setting this bit and bit 1 simultaneously high will hold the pclk2 pin low. reference: section 3.7.1 on page 52 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 74 of 95 pclk3_phase/divide 2eh 15-6 reserved. set thes e bits to zero when writing to 2eh. ? ? 2eh 5-2 pclk3_phase - adjusts the output phase of the pclk3/pclk3 clock with respect to the timing output pins. phase is delayed in 700ps (nominal) increments as shown in table 3-6 . reference: section 3.7.1 on page 52 r/w 0 2eh 1 divide_by_4 - set this bit high to divide the output pclk3/pclk3 by four. setting this bit and bit 0 simultaneously high will give the full rate video clock on the pclk3 / pclk3 pins. reference: section 3.7.1 on page 52 r/w 0 2eh 0 divide_by_2 - set this bit high to divide the output pclk3/pclk3 by two. setting this bit and bit 1 simultaneously high will give the full rate video clock on the pclk3 / pclk3 pins. reference: section 3.7.1 on page 52 r/w 0 pclk3_tristate 2fh 15-2 reserved. set these bits to zero when writing to 2fh. ? ? 2fh 1-0 set these bits to 11b to tristate the pclk3 / pclk3 pins. reference: section 3.7.1 on page 52 r/w 00b rsvd 2fh - 30h ? reserved. ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 75 of 95 audio_control (gs4901b only) 31h 15-10 reserved. set these bits to zero when writing to 31h. ? ? 31h 9-7 afs_reset_window - these bits may be used to adjust the value by which the audi o clock counters are allowed to drift from the output afs pulse. the encoding scheme for this register is shown in table 3-9 . note: the default setting of th is register will provide a reset window that is sufficient for most standards. to maintain correct audio clock frequencies for some vesa standards, the reset window may have to be increased from its default setting. in this case, set the value of this register to 1xx. see table 3-9 . reference: section 3.7.2 on page 53 r/w 010b 31h 6 reserved. set this it to zero when writing to 31h. r/w 0 31h 5 enable_384fs - set this bit high to enable the 384fs and 192fs audio clock outputs. this must be set in addition to registers 3fh to 41h. note: if this bit is high, then a 512fs audio clock will have a 33% duty cycle when fs = 96khz. reference: section 3.7.2 on page 53 r/w 0 31h 4-3 reserved. set these bits to zero when writing to 31h. ? ? 31h 2 host_asr_sel - set this bit high to select the audio sample rate using register 32h instead of the external asr_sel[2:0] pins. the external asr_sel[2:0] pins will be ignored, but should not be left floating. reference: section 3.7.2 on page 53 r/w 0 31h 1 afs_f_pulse - set this bit to 1 to stretch the afs pulse duration from 1 line to 1 field. reference: section 3.8.2 on page 58 r/w 0 31h 0 afs_reset_disable - set this bit high to disable the 10fid input reference pin from resetting the output afs pulse. if this bit is set high, the output afs pulse will free-run or may be reset using register 1ah. the external 10fid pin should not be left floating. reference: section 3.8.2 on page 58 r/w 0 asr_sel[2:0] (gs4901b only) 32h 15-3 reserved. set these bits to zero when writing to 32h. ? ? 32h 2-0 replaces the external asr_sel[2:0] pins when host_asr_select (bit 2 of address 31h) is high. the default setting of this register corresponds to an audio sample rate of 48khz. reference: section 3.7.2 on page 53 r/w 011b rsvd 33h - 38h ? reserved. ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 76 of 95 audio_cap_genlock (gs4901b only) 39h 15-6 reserved. set these bits to zero when writing to 39h. ? ? 39h 5-0 control signal to adjust loop bandwidth of audio genlock block. the value programmed in this register must be between 10 and audio_res_genlock - 21. the default value of this register will depend on the fundamental sampling frequency selected. reference: section 3.6.2 on page 48 r/w ? audio_res_genlock (gs4901b only) 3ah 15-6 reserved. set these bits to zero when writing to 3ah. ? ? 3ah 5-0 control signal to adjust loop bandwidth of audio genlock block. the value programmed in this register must be between 32 and 42. the default value of this register will depend on the fundamental sampling frequency selected. reference: section 3.6.2 on page 48 r/w ? rsvd 3bh-3eh ? reserved ? ? aclk1_fs_multiple (gs4901b only) 3fh 15-3 reserved. set these bits to zero when writing to 3fh. ? ? 3fh 2-0 the user may set this register to select the desired frequency of the audio clock on aclk1 (a multiple of the fundamental sampling rate, fs). the audio clock frequency may be set as: 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs, or z-bit. see table 3-8 for more details. note: to output a frequency of 348fs or 192fs, bit 5 of register 31h must also be set high. reference: section 3.7.2 on page 53 r/w 0 aclk2_fs_multiple (gs4901b only) 40h 15-3 reserved. set these bits to zero when writing to 40h. ? ? 40h 2-0 the user may set this register to select the desired frequency of the audio clock on aclk2 (a multiple of the fundamental sampling rate, fs). the audio clock frequency may be set as: 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs, or z-bit. see table 3-8 for more details. note: to output a frequency of 348fs or 192fs, bit 5 of register 31h must also be set high. reference: section 3.7.2 on page 53 r/w 0 aclk3_fs_multiple (gs4901b only) 41h 15-3 reserved. set these bits to zero when writing to 41h. ? ? 41h 2-0 the user may set this register to select the desired frequency of the audio clock on aclk3 (a multiple of the fundamental sampling rate, fs). the audio clock frequency may be set as: 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs, or z-bit. see table 3-8 for more details. note: to output a frequency of 348fs or 192fs, bit 5 of register 31h must also be set high. reference: section 3.7.2 on page 53 r/w 0 rsvd 42h ? reserved. ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 77 of 95 output_select_1 43h 15-5 reserved. set these bits to zero when writing to 43h. ? ? 43h 4 current_1 - selects the current drive capability of the timing_out_1 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 43h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_1 pin. see table 3-11 for more details. note: the default setting of this register is 0001b, which corresponds to h sync. reference: section 3.8.4 on page 61 r/w 0001b output_select_2 44h 15-5 reserved. set these bits to zero when writing to 44h. ? ? 44h 4 current_2 - selects the current drive capability of the timing_out_2 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 44h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_2 pin. see table 3-11 for more details. note: the default setting of this register is 0010b, which corresponds to h blanking. reference: section 3.8.4 on page 61 r/w 0010b output_select_3 45h 15-5 reserved. set these bits to zero when writing to 45h. ? ? 45h 4 current_3 - selects the current drive capability of the timing_out_3 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 45h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_3 pin. see table 3-11 for more details. note: the default setting of this register is 0011b, which corresponds to v sync. reference: section 3.8.4 on page 61 r/w 0011b output_select_4 46h 15-5 reserved. set these bits to zero when writing to 46h. ? ? 46h 4 current_4 - selects the current drive capability of the timing_out_4 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 46h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_4 pin. see table 3-11 for more details. note: the default setting of this register is 0100b, which corresponds to v blanking. reference: section 3.8.4 on page 61 r/w 0100b table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 78 of 95 output_select_5 47h 15-5 reserved. set these bits to zero when writing to 47h. ? ? 47h 4 current_5 - selects the current drive capability of the timing_out_5 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 47h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_5 pin. see table 3-11 for more details. note: the default setting of this register is 0101b, which corresponds to f sync. reference: section 3.8.4 on page 61 r/w 0101b output_select_6 48h 15-5 reserved. set these bits to zero when writing to 48h. ? ? 48h 4 current_6 - selects the current drive capability of the timing_out_6 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 48h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_6 pin. see table 3-11 for more details. note: the default setting of this register is 0110b, which corresponds to f digital. reference: section 3.8.4 on page 61 r/w 0110b output_select_7 49h 15-5 reserved. set these bits to zero when writing to 49h. ? ? 49h 4 current_7 - selects the current drive capability of the timing_out_7 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 49h 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_7 pin. see table 3-11 for more details. note: the default setting of this register is 0111b, which corresponds to 10fid. reference: section 3.8.4 on page 61 r/w 0111b output_select_8 4ah 15-5 reserved. set these bits to zero when writing to 4ah. ? ? 4ah 4 current_8 - selects the current drive capability of the timing_out_8 pin. set this bit high for high current drive. otherwise, the current drive will be low. reference: section 3.8.4 on page 61 r/w 0 4ah 3-0 this register is used to select one of the 10 pre-programmed or 4 user programmed timing signals available for output on the timing_out_8 pin. see table 3-11 for more details. note: the default setting of this register is 1000b, which corresponds to display enable (de). reference: section 3.8.4 on page 61 r/w 1000b table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 79 of 95 rsvd 4bh ? reserved. ? ? video_control 4ch 15-5 reserved. set these bits to zero when writing to 4ch. ? ? 4ch 4 10fid_f_pulse - set this bit high to stretch the 10fid pulse duration from 1 line to 1 field. reference: section 3.8.1 on page 57 r/w 0 4ch 3-2 reserved. set these bits to zero when writing to 4ch. ? ? 4ch 1 host_vid_std - set this bit high to select the output video standard using register 4dh instead of the external vid_std[5:0] pins. the external vid_std[5:0] pins will be ignored, but should not be left floating. reference: section 1.4 on page 20 r/w 0 4ch 0 reserved. set this bit to zero when writing to 4ch. ? ? vid_std[5:0] 4dh 15-6 reserved. set these bits to zero when writing to 4dh. ? ? 4dh 5-0 replaces the external vid_std[5:0] pins when vid_from_host (bit 1 of address 4ch) is high. reference: section 1.4 on page 20 r/w 00h rsvd 4eh-55h ? reserved ? ? polarity 56h 15-10 reserved. set these bits to zero when writing to 56h. ? ? 56h 9 afs (gs4901b only)- set this bit high to invert the polarity of the afs timing output signal. by default, the afs signal is high for the duration of the first line of the n?th video frame to indicate that the aclk dividers have been reset at the start of line 1 of that frame. note: the GS4900B does not generate an afs pulse and will ignore the setting of this bit. reference: table 1-3 r/w 0 56h 8 10fid - set this bit high to invert the polarity of the 10fid timing output signal. by default, the 10fid signal will go high for one line at the start of the 10-field sequence. reference: table 1-3 r/w 0 56h 7 de - set this bit high to invert the polarity of the de timing output signal. by default, the de signal will be high whenever pixel information is to be displayed on the display device reference: table 1-3 r/w 0 56h 6 reserved. set this bit to zero when writing to 56h. ? ? 56h 5 f_digital - set this bit high to invert the polarity of the f digital timing output signal. by default, the f digital signal will be high for the entire period of field 1. reference: table 1-3 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 80 of 95 56h 4 f_sync - set this bit high to invert the polarity of the f sync timing output signal. by default, the f sync signal will be high for the entire period of field 1. reference: table 1-3 r/w 0 56h 3 v_blanking - set this bit high to invert the polarity of the v blanking timing output signal. by default, the v blanking sig nal will be low for the portion of the field/frame containing valid video data. reference: table 1-3 r/w 0 56h 2 v_sync - set this bit high to invert the polarity of the v sync timing output signal. by default, the v sync signal is active low. reference: table 1-3 r/w 0 56h 1 h_blanking - set this bit high to invert the polarity of the h blanking timing output signal. by default, the h blanking signal will be low for the portion of the video line containing valid video samples. reference: table 1-3 r/w 0 56h 0 h_sync - set this bit high to invert the polarity of the h sync timing output signal. by default, the h sync signal is active low. reference: table 1-3 r/w 0 h_start_1 57h 15-0 the value programmed in this register indicates the pixel start point for the leading edge of the user-programmed h sync signal user1_h. note: the value programmed in this register must be less than the value programmed in h_stop_1. reference: section 3.8.3 on page 59 r/w 0 h_stop_1 58h 15-0 the value programmed in this register indicates the pixel end point for the trailing edge of the user-programmed h sync signal user1_h. note: the value programmed in this register must not exceed the maximum number of clock periods per line of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 v_start_1 59h 15 reserved. set this bit to zero when writing to 59h. ? ? 59h 14-0 the value programmed in this register indicates the start line number of the leading edge of the user-programmed v sync signal user1_v. for interlaced output standards, this value corresponds to the odd field number. note: the value programmed in this register must be less than the value programmed in v_stop_1. reference: section 3.8.3 on page 59 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 81 of 95 v_stop_1 5ah 15 reserved. set this bit to zero when writing to 5ah. ? ? 5ah 14-0 the value programmed in th is register indicates the end line number of the trailing edge of the user-programmed v sync signal user1_v. for interlaced output standards, this value corresponds to the odd field number. note: the value programmed in this register must not exceed the maximum number of lines per field of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 operator_polarity_1 5bh 15-4 reserved. set t hese bits to zero when writing to 5bh. ? ? 5bh 3 polarity_1 - use this bit to invert the polarity of the final user1 signal. by default, the polarity of the user programmed signals is active low. the polarity may be switched to active high by setting this bit low. reference: section 3.8.3 on page 59 r/w 1 5bh 2 and_1 - logical operator: user1_h and user1_v set this bit high to output a signal that is only active when both user1_h and user1_v are active. when this bit is high, bit 1 and bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 5bh 1 or_1 - logical operator: user1_h or user1_v set this bit high to output a signal that is active whenever user1_h or user1_v are active. when this bit is high bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 5bh 0 xor_1 - logical operator: user1_h xor user1_v set this bit high to output a signal with the following attributes: signal becomes active when either user1_h or user1_v is active. signal is inactive when user1_h and user1_v are both active or both inactive. reference: section 3.8.3 on page 59 r/w 0 h_start_2 5ch 15-0 the value programmed in this register indicates the pixel start point for the leading edge of the user-programmed h sync signal user2_h. note: the value programmed in this register must be less than the value programmed in h_stop_2 reference: section 3.8.3 on page 59 r/w 0 h_stop_2 5dh 15-0 the value programmed in this register indicates the pixel end point for the trailing edge of the user-programmed h sync signal user2_h. note: the value programmed in this register must not exceed the maximum number of clock periods per line of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 82 of 95 v_start_2 5eh 15 reserved. set this bit to zero when writing to 5eh. ? ? 5eh 14-0 the value programmed in this register indicates the start line number of the leading edge of the user-programmed v sync signal user2_v. for interlaced output standards, this value corresponds to the odd field line number. note: the value programmed in this register must be less than the value programmed in v_stop_2. reference: section 3.8.3 on page 59 r/w 0 v_stop_2 5fh 15 reserved. set this bit to zero when writing to 5fh. ? ? 5fh 14-0 the value programmed in th is register indicates the end line number of the trailing edge of the user-programmed v sync signal user2_v. for interlaced output standards, this value corresponds to the odd field line number. note: the value programmed in this register must not exceed the maximum number of lines per field of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 operator_polarity_2 60h 15-4 reserved. set t hese bits to zero when writing to 60h. ? ? 60h 3 polarity_2 - use this bit to invert the polarity of the final user2 signal. by default, the polarity of the user programmed signals is active low. the polarity may be switched to active high by setting this bit low. reference: section 3.8.3 on page 59 r/w 1 60h 2 and_2 - logical operator: user2_h and user2_v set this bit high to output a signal that is only active when both user2_h and user2_v are active. when this bit is high, bit 1 and bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 60h 1 or_2 - logical operator: user2_h or user2_v set this bit high to output a signal that is active whenever user2_h or user2_v are active. when this bit is high bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 60h 0 xor_2 - logical operator: user2_h xor user2_v set this bit high to output a signal with the following attributes: signal becomes active when either user2_h or user2_v is active. signal is inactive when user2_h and user2_v are both active or both inactive. reference: section 3.8.3 on page 59 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 83 of 95 h_start_3 61h 15-0 the value programmed in this register indicates the pixel start point for the leading edge of the user-programmed h sync signal user3_h. note: the value programmed in this register must be less than the value programmed in h_stop_3. reference: section 3.8.3 on page 59 r/w 0 h_stop_3 62h 15-0 the value programmed in this register indicates the pixel end point for the trailing edge of the user-programmed h sync signal user3_h. note: the value programmed in this register must not exceed the maximum number of clock periods per line of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 v_start_3 63h 15 reserved. set this bit to zero when writing to 63h. ? ? 63h 14-0 the value programmed in this register indicates the start line number of the leading edge of the user-programmed v sync signal user3_v. for interlaced output standards, this value corresponds to the odd field line number. note: the value programmed in this register must be less than the value programmed in v_stop_3. reference: section 3.8.3 on page 59 r/w 0 v_stop_3 64h 15 reserved. set this bit to zero when writing to 64h. ? ? 64h 14-0 the value programmed in this register indicates the end line number of the trailing edge of the user-programmed v sync signal user3_v. for interlaced output standards, this value corresponds to the odd field line number. note: the value programmed in this register must not exceed the maximum number of lines per field of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 84 of 95 operator_polarity_3 65h 15-4 reserved. set t hese bits to zero when writing to 65h. ? ? 65h 3 polarity_3 - use this bit to invert the polarity of the final user3 signal. by default, the polarity of the user programmed signals is active low. the polarity may be switched to active high by setting this bit low. reference: section 3.8.3 on page 59 r/w 1 65h 2 and_3 - logical operator: user3_h and user3_v set this bit high to output a signal that is only active when both user3_h and user3_v are active. when this bit is high, bit 1 and bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 65h 1 or_3 - logical operator: user3_h or user3_v set this bit high to output a signal that is active whenever user3_h or user3_v are active. when this bit is high bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 65h 0 xor_3 - logical operator: user3_h xor user3_v set this bit high to output a signal with the following attributes: signal becomes active when either user3_h or user3_v is active. signal is inactive when user3_h and user3_v are both active or both inactive. reference: section 3.8.3 on page 59 r/w 0 h_start_4 66h 15-0 the value programmed in this register indicates the pixel start point for the leading edge of the user-programmed h sync signal user4_h. note: the value programmed in this register must be less than the value programmed in h_stop_4. reference: section 3.8.3 r/w 0 h_stop_4 67h 15-0 the value programmed in this register indicates the pixel end point for the trailing edge of the user-programmed h sync signal user4_h. note: the value programmed in this register must not exceed the maximum number of clock periods per line of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 v_start_4 68h 15 reserved. set this bit to zero when writing to 68h. ? ? 68h 14-0 the value programmed in this register indicates the start line number of the leading edge of the user-programmed v sync signal user4_v. for interlaced output standards, this value corresponds to the odd field line number. note: the value programmed in this register must be less than the value programmed in v_stop_4. reference: section 3.8.3 on page 59 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 85 of 95 v_stop_4 69h 15 reserved. set this bit to zero when writing to 69h. ? ? 69h 14-0 the value programmed in this register indicates the end line number of the trailing edge of the user-programmed v sync signal user4_v. for interlaced output standards, this value corresponds to the odd field line number. note: the value programmed in this register must not exceed the maximum number of lines per field of the outgoing standard. reference: section 3.8.3 on page 59 r/w 0 operator_polarity_4 6ah 15-4 reserved. set t hese bits to zero when writing to 6ah. ? ? 6ah 3 polarity_4 - use this bit to invert the polarity of the final user4 signal. by default, the polarity of the user programmed signals is active low. the polarity may be switched to active high by setting this bit low. reference: section 3.8.3 on page 59 r/w 1 6ah 2 and_4 - logical operator: user4_h and user4_v set this bit high to output a signal that is only active when both user4_h and user4_v are active. when this bit is high, bit 1 and bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 6ah 1 or_4 - logical operator: user4_h or user4_v set this bit high to output a signal that is active whenever user4_h or user4_v are active. when this bit is high bit 0 of this register will be ignored. reference: section 3.8.3 on page 59 r/w 0 6ah 0 xor_4 - logical operator: user4_h xor user4_v set this bit high to output a signal with the following attributes: signal becomes active when either user4_h or user4_v is active. signal is inactive when user4_h and user4_v are both active or both inactive. reference: section 3.8.3 on page 59 r/w 0 ext_audio_mode 81h 15-0 set this register to 20c1h to enable the extended audio mode of the device. to fully enable this mode, vid_std[5:0] must be set to 4d, and the f_lock_mask and v_lock_mask bits [4:3] of register address 16h must be set to 1. note: once this register is programmed, it must be updated using bit 6 of register 16h. reference: section 3.9 on page 62 r/w 0 table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 86 of 95 hd_reference_enable 82h 15-8 reserved. set these bits to zero when writing to 82h. ? ? 82h 7 hd_ref_enable - set this bi t high to allow the device to recognize the hd input reference formats that have also been enabled in the reference_standard_disable register (address 11h-13h). when this bit is set high , the gs4901b/GS4900B will only assert ref_lost when the input signal is removed. reference: section 3.5 on page 42 . r/w 0 82h 6-0 reserved. set these bits to zero when writing to 82h. ? ? ln_count_reset 83h 15 toggle this bit to reset the line-based counters in the device. this is only required when locking the 525-line sd output standards to the ?f/1.001? hd input reference standards, and: 1. the reference has been removed and subsequently re-applied. in this case, the user should wait until the reference has been re-detected by the device, which may take up to 4 frames. see section 3.5.3 on page 44 . or 2. the device is locked to blanking signals from a deserializer, and the sdi input to the deserializer has been switched upstream from the system. see section 3.6.3 on page 51 . r/w 0 83h 14-0 reserved. set these bits to zero when writing to 83h. ? ? table 3-13: configuration and status registers (continued) register name address bit description r/w default
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 87 of 95 3.11 jtag when the jtag/host input pin of the gs4901b/GS4900B is set high, the host interface port will be configured for jtag test operation. in this mode, pins 57 through 60 become tclk , tdi, tdo, and tms. in addition, the reset pin will operate as the test reset pin. boundary scan testing using the jtag interface will be enabl ed in this mode. there are two methods in which jtag can be used on the gs4901b/GS4900B: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applications such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the te sts are to be applied only at ate, this can be accomplished with high-impedance buffers used in conjunction with the jtag/host input signal. this is shown in figure 3-16 . figure 3-16: in-circuit jtag alternatively, if the test ca pabilities are to be used in the system, the host may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 3-17 . application host gs4911b/gs4910b cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host in-circuit ate probe
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 88 of 95 figure 3-17: system jtag 3.12 device power-up 3.12.1 power suppl y sequencing the gs4901b/GS4900B has a recommended power supply sequence. to ensure correct power-up, the analog_vdd and core_vdd power pins should be powered before io_vdd. device pins may be driven prior to power-up without causing damage. 3.13 device reset in order to initialize operatin g conditions to their default states, the application layer must hold the reset signal low during power up and for a minimum of 500us after the last supply has reached its operating voltage. application host gs4911b/gs4910b cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host in-circuit ate probe tri-state
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 89 of 95 4. application reference design 4.1 gs4901b typical application circuit note: for a solution with the lowest output jitter, the gs9062 or gs9092a serializers are recommended for use with the gs4901b/GS4900B. controlled impedance 100-ohms differential note: the gs4911a inputs are 5v tolerant for 3v3 i/o operation only (io_vdd=3v3) the 10fid input must be grounded if it will not be used vid_pll_gnd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_gnd 8 core_gnd 9 phs_gnd 55 phs_vdd 54 analog_vdd 10 nc 11 analog_gnd 12 aud_pll_gnd 13 aud_pll_vdd 14 10fid 15 hsync 16 vsync 17 io_vdd 18 fsync 19 nc 20 vid_std0 21 vid_std1 22 vid_std2 23 vid_std3 24 vid_std4 25 vid_std5 27 aclk1 28 aclk2 29 aclk3 30 io_vdd 31 core_vdd 26 asr_sel2 32 asr_sel1 33 asr_sel0 34 timing_out1 35 timing_out2 36 io_vdd 38 timing_out4 39 timing_out3 37 timing_out5 40 lvds/pclk3_vdd 45 pclk3 46 lvds/pclk3_gnd 48 pclk3 47 pclk2 49 pclk1&2_gnd 52 pclk1 51 io_vdd 50 timing_out6 41 timing_out7 42 timing_out8 43 pclk1&2_vdd 53 lock_lost 1 ref_lost 2 genlock 64 core_vdd 44 jtag/host 56 sclk_tclk 57 sdin_tdi 58 sdout_tdo 59 cs_tms 60 reset 61 io_vdd 62 nc 63 gnd_pad 65 22r 10n 10n 10n 10n 22r 22r 22r 22r 10n 0r 22r 10n 22r 24pf 10n 22r 22r gs4901b 10n 38pf 10n 22r 22r 10n 10n 1m 22r 10n 10n 22r 1v8_pclk vdd_io 1v8_core gnd_xtal 1v8_core vdd_io vdd_io 1v8_vpll 1v8_vpll gnd_vpll 1v8_pclk vdd_io gnd_vpll 1v8_apll gnd_apll vdd_xtal gnd_xtal hsync vsync fsync 10fid aclk3 aclk2 aclk1 timing 1 timing 2 timing 3 timing 4 timing 5 timing 6 timing 7 timing 8 csb resetb sdin sdout sclk pclk2 pclk3 pclk3 b pclk1 genlockb j tag/hostb vid_std0 vid_std1 vid_std2 vid_std3 asr_sel0 asr_sel2 asr_sel1 lock_lost ref_lost 27mhz
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 90 of 95 4.2 GS4900B typical application circuit note: for a solution with the lowest output jitter, the gs9062 or gs9092a serializers are recommended for use with the gs4901b/GS4900B. controlled impedance 100-ohms differential note: the gs4910a inputs are 5v tolerant for 3v3 i/o operation only (io_vdd=3v3) the 10fid input must be grounded if it will not be used vid_pll_gnd 4 vid_pll_vdd 3 xtal_vdd 5 x1 6 x2 7 xtal_gnd 8 core_gnd 9 phs_gnd 55 phs_vdd 54 analog_vdd 10 nc 11 analog_gnd 12 analog_gnd 13 analog_gnd 14 10fid 15 hsync 16 vsync 17 io_vdd 18 fsync 19 nc 20 vid_std0 21 vid_std1 22 vid_std2 23 vid_std3 24 vid_std4 25 vid_std5 27 nc 28 nc 29 nc 30 io_vdd 31 core_vdd 26 analog_gnd 32 analog_gnd 33 analog_gnd 34 timing_out1 35 timing_out2 36 io_vdd 38 timing_out4 39 timing_out3 37 timing_out5 40 lvds/pclk3_vdd 45 pclk3 46 lvds/pclk3_gnd 48 pclk3 47 pclk2 49 pclk1&2_gnd 52 pclk1 51 io_vdd 50 timing_out6 41 timing_out7 42 timing_out8 43 pclk1&2_vdd 53 lock_lost 1 ref_lost 2 genlock 64 core_vdd 44 jtag/host 56 sclk_tclk 57 sdin_tdi 58 sdout_tdo 59 cs_tms 60 reset 61 io_vdd 62 nc 63 gnd_pad 65 10n 10n 10n 10n 22r 22r 22r 10n 0r 10n 24pf 22r 10n 22r 22r GS4900B 10n 38pf 10n 22r 10n 22r 1m 10n 22r 10n 10n 22r 1v8_pclk vdd_io 1v8_core gnd_xtal 1v8_core vdd_io vdd_io 1v8_vpll 1v8_vpll gnd_vpll 1v8_pclk vdd_io gnd_vpll gnd_a vdd_xtal gnd_xtal 1v8_a gnd_a gnd_a hsync vsync fsync 10fid timing 1 timing 2 timing 3 timing 4 timing 5 timing 6 timing 7 timing 8 csb resetb sdin sdout sclk pclk2 pclk3 pclk3 b pclk1 genlockb jtag/hostb v id_std0 v id_std1 v id_std2 v id_std3 lock_lost ref_lost 27mhz
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 91 of 95 5. references & relevant standards table 5-1: references & relevant standards aes11-1997 synchronization of digital au dio equipment in studio operations smpte 125m-1995 component video signal 4:2:2 ? bit-parallel digital interface smpte 170m-1999 composite analog video si gnal ? ntsc for studio applications smpte 244m-1995 system m/ntsc composit e video signals ? bit-parallel digital interface smpte 260m-1999 1125/60 high-definition produc tion system ? digital representation and bit-parallel interface smpte 267m-1995 bit-parallel digital interface ? component video signal 4:2:2 16x9 aspect ratio smpte 274m-1998 1920 x 1080 scanning and analog and parallel digital interfaces for multiple picture rates smpte 293m-1996 720 x 483 active line at 59.94-hz progressive scan production ? digital representation smpte 296m-1997 1280 x 720 scanning, analog and digital representation an analog interface smpte 318m-1999 synchronization of 59.94- or 50-hz related video and audio systems in analog and digital areas ? reference signals smpte 347m-2001 540 mb/s serial digital in terface ? source image format mapping smpte rp 164-1996 location of vertical interval time code smpte rp 168-1993 definition of vertical in terval switching point for synchronous video switching smpte rp 211-2000 implementation of 24p, 25p and 30p segmented frames for 1920 x 1080 production format itu-r bt.601-5 studio encoding parameters of digital television for standard 4:3 and wide-screen 16:9 aspect ratios itu-r bt.709-4 parameter values for the hdtv standards for production and international program exchange itu-r bt.799.3 interface for digital component video signals in 525-line and 625-line television systems operating at the 4:4:4 level of recommendation itu-r bt.601 (part a) itu-r bt.1358 studio parameters of 625 and 525 line progressive scan television systems vesa monitor timing specifications vesa and industry standards and guidelines for computer display monitor timing ? version 1.0, revi sion 0.8 (adoption date: september 17, 1998)
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 92 of 95 6. package & ordering information 6.1 package dimensions a b 9 . 00 4. 50 4 . 50 9 . 00 2 x 2x 0 .1 5 c 0 . 15 c 0 . 10 c 0.08 c 64 x s eatin g plan e 0 .90 + / - 0.10 + 0 . 03 0 . 02 - 0 . 02 0 .2 0 ref c 7 .10+/-0.15 3 .5 5 0.40+ / -0.0 5 0 .95+/-0.05 7 .10+/-0.15 3 .5 5 + 0 . 03 0 .2 5 - 0 . 0 2 64 x 0 . 10 c a b c 0 . 05 0 .5 0 all dimen s i o n s in m m pin 1 area centre tab 4 .50
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 93 of 95 6.2 recommended pcb footprint the center pad of the pcb footprint should be connected to the ground plane by a minimum of 36 vias. note: suggested dimensions only. final dimensions should conform to customer design rules and process optimizations. 6.3 packaging data note: all dimensio ns are in millimeters. 7.10 7.10 8.70 8 .70 0.50 0.25 0.55 center pad parameter value package type 9mm x 9mm 64-pin qfn moisture sensitivity level 3 junction to case thermal resistance, j-c 9.3c/w junction to air thermal resistance, j-a (at zero airflow) 24.6c/w psi, 0.2c/w pb-free and rohs compliant yes
gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 94 of 95 6.4 ordering information part video clocks audio clocks max pclk rate gs4901b ? 54mhz GS4900B ? 54mhz part number package temperature range gs4901bcne3 pb-free 64-pin qfn 0c to 70c GS4900Bcne3 pb-free 64-pin qfn 0c to 70c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2006 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs4901b/GS4900B prelim inary data sheet 37703 - 0 april 2006 95 95 of 95 document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change without notice. 7. revision history version ecr pcn date changes and/or modifications a 138810 ? january 2006 new document. 0 140153 ? april 2006 converting to preliminary data sheet. corrected loop bandwidth calculations. updated description of locking to hd formats. updated power consumption.

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